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| 1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
| 4 // met: | 4 // met: |
| 5 // | 5 // |
| 6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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| 478 | 478 |
| 479 void MacroAssembler::PopSafepointRegistersAndDoubles() { | 479 void MacroAssembler::PopSafepointRegistersAndDoubles() { |
| 480 for (int i = 0; i < DwVfpRegister::kNumAllocatableRegisters; i++) { | 480 for (int i = 0; i < DwVfpRegister::kNumAllocatableRegisters; i++) { |
| 481 vldr(DwVfpRegister::FromAllocationIndex(i), sp, i * kDoubleSize); | 481 vldr(DwVfpRegister::FromAllocationIndex(i), sp, i * kDoubleSize); |
| 482 } | 482 } |
| 483 add(sp, sp, Operand(DwVfpRegister::kNumAllocatableRegisters * | 483 add(sp, sp, Operand(DwVfpRegister::kNumAllocatableRegisters * |
| 484 kDoubleSize)); | 484 kDoubleSize)); |
| 485 PopSafepointRegisters(); | 485 PopSafepointRegisters(); |
| 486 } | 486 } |
| 487 | 487 |
| 488 void MacroAssembler::StoreToSafepointRegistersAndDoublesSlot(Register reg) { | 488 void MacroAssembler::StoreToSafepointRegistersAndDoublesSlot(Register src, |
| 489 str(reg, SafepointRegistersAndDoublesSlot(reg)); | 489 Register dst) { |
| 490 str(src, SafepointRegistersAndDoublesSlot(dst)); |
| 490 } | 491 } |
| 491 | 492 |
| 492 | 493 |
| 493 void MacroAssembler::StoreToSafepointRegisterSlot(Register reg) { | 494 void MacroAssembler::StoreToSafepointRegisterSlot(Register src, Register dst) { |
| 494 str(reg, SafepointRegisterSlot(reg)); | 495 str(src, SafepointRegisterSlot(dst)); |
| 495 } | 496 } |
| 496 | 497 |
| 497 | 498 |
| 498 void MacroAssembler::LoadFromSafepointRegisterSlot(Register reg) { | 499 void MacroAssembler::LoadFromSafepointRegisterSlot(Register dst, Register src) { |
| 499 ldr(reg, SafepointRegisterSlot(reg)); | 500 ldr(dst, SafepointRegisterSlot(src)); |
| 500 } | 501 } |
| 501 | 502 |
| 502 | 503 |
| 503 int MacroAssembler::SafepointRegisterStackIndex(int reg_code) { | 504 int MacroAssembler::SafepointRegisterStackIndex(int reg_code) { |
| 504 // The registers are pushed starting with the highest encoding, | 505 // The registers are pushed starting with the highest encoding, |
| 505 // which means that lowest encodings are closest to the stack pointer. | 506 // which means that lowest encodings are closest to the stack pointer. |
| 506 ASSERT(reg_code >= 0 && reg_code < kNumSafepointRegisters); | 507 ASSERT(reg_code >= 0 && reg_code < kNumSafepointRegisters); |
| 507 return reg_code; | 508 return reg_code; |
| 508 } | 509 } |
| 509 | 510 |
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| 2549 void CodePatcher::EmitCondition(Condition cond) { | 2550 void CodePatcher::EmitCondition(Condition cond) { |
| 2550 Instr instr = Assembler::instr_at(masm_.pc_); | 2551 Instr instr = Assembler::instr_at(masm_.pc_); |
| 2551 instr = (instr & ~kCondMask) | cond; | 2552 instr = (instr & ~kCondMask) | cond; |
| 2552 masm_.emit(instr); | 2553 masm_.emit(instr); |
| 2553 } | 2554 } |
| 2554 | 2555 |
| 2555 | 2556 |
| 2556 } } // namespace v8::internal | 2557 } } // namespace v8::internal |
| 2557 | 2558 |
| 2558 #endif // V8_TARGET_ARCH_ARM | 2559 #endif // V8_TARGET_ARCH_ARM |
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