ARM: Enable loads and stores of VFP registers with offsets >= 1024 bytes.

src/arm/assembler-arm.h

Index: src/arm/assembler-arm.h
===================================================================
--- src/arm/assembler-arm.h	(revision 6826)
+++ src/arm/assembler-arm.h	(working copy)
@@ -387,7 +387,7 @@
   // Return true if this is a register operand.
   INLINE(bool is_reg() const);
 
-  // Return true of this operand fits in one instruction so that no
+  // Return true if this operand fits in one instruction so that no
   // 2-instruction solution with a load into the ip register is necessary.
   bool is_single_instruction() const;
   bool must_use_constant_pool() const;
@@ -439,7 +439,7 @@
       offset_ = offset;
   }
 
-  uint32_t offset() {
+  uint32_t offset() const {
       ASSERT(rm_.is(no_reg));
       return offset_;
   }
@@ -447,6 +447,10 @@
   Register rn() const { return rn_; }
   Register rm() const { return rm_; }
 
+  bool OffsetIsEncodable() const {

[Rodolph Perfetta, 2011/02/16 16:48:54]

load/store word and byte support a 12bits offset but load/store halfword and
signed byte support a smaller offset. Furthermore this patch add support for
vldr/vstr and there the offset is 8bits (shifted left by 2 to get the value).

[William Hesse, 2011/02/17 11:27:29]

Changed name to OffsetIsUint12Encodable On 2011/02/16 16:48:54, Rodolph Perfetta
wrote:

+    return offset_ >= 0 ? is_uint12(offset_) : is_uint12(-offset_);
+  }
+
  private:
   Register rn_;  // base
   Register rm_;  // register offset
@@ -902,23 +906,35 @@
 
   void vldr(const DwVfpRegister dst,
             const Register base,
-            int offset,  // Offset must be a multiple of 4.
+            int offset,
             const Condition cond = al);
+  void vldr(const DwVfpRegister dst,
+            const MemOperand& src,
+            const Condition cond = al);
 
   void vldr(const SwVfpRegister dst,
             const Register base,
-            int offset,  // Offset must be a multiple of 4.
+            int offset,
             const Condition cond = al);
+  void vldr(const SwVfpRegister dst,
+            const MemOperand& src,
+            const Condition cond = al);
 
   void vstr(const DwVfpRegister src,
             const Register base,
-            int offset,  // Offset must be a multiple of 4.
+            int offset,
             const Condition cond = al);
+  void vstr(const DwVfpRegister src,
+            const MemOperand& dst,
+            const Condition cond = al);
 
   void vstr(const SwVfpRegister src,
             const Register base,
-            int offset,  // Offset must be a multiple of 4.
+            int offset,
             const Condition cond = al);
+  void vstr(const SwVfpRegister src,
+            const MemOperand& dst,
+            const Condition cond = al);
 
   void vmov(const DwVfpRegister dst,
             double imm,