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Issue 6368053: Implements DoubleToI on ARM. Refactor some VFP code at the same time and... (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: '' Created 9 years, 10 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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935 void vmov(const Register dst1, 935 void vmov(const Register dst1,
936 const Register dst2, 936 const Register dst2,
937 const DwVfpRegister src, 937 const DwVfpRegister src,
938 const Condition cond = al); 938 const Condition cond = al);
939 void vmov(const SwVfpRegister dst, 939 void vmov(const SwVfpRegister dst,
940 const Register src, 940 const Register src,
941 const Condition cond = al); 941 const Condition cond = al);
942 void vmov(const Register dst, 942 void vmov(const Register dst,
943 const SwVfpRegister src, 943 const SwVfpRegister src,
944 const Condition cond = al); 944 const Condition cond = al);
945 enum ConversionMode {
946 FPSCRRounding = 0,
947 RoundToZero = 1
948 };
949 void vcvt_f64_s32(const DwVfpRegister dst, 945 void vcvt_f64_s32(const DwVfpRegister dst,
950 const SwVfpRegister src, 946 const SwVfpRegister src,
951 ConversionMode mode = RoundToZero, 947 VFPConversionMode mode = kDefaultRoundToZero,
952 const Condition cond = al); 948 const Condition cond = al);
953 void vcvt_f32_s32(const SwVfpRegister dst, 949 void vcvt_f32_s32(const SwVfpRegister dst,
954 const SwVfpRegister src, 950 const SwVfpRegister src,
955 ConversionMode mode = RoundToZero, 951 VFPConversionMode mode = kDefaultRoundToZero,
956 const Condition cond = al); 952 const Condition cond = al);
957 void vcvt_f64_u32(const DwVfpRegister dst, 953 void vcvt_f64_u32(const DwVfpRegister dst,
958 const SwVfpRegister src, 954 const SwVfpRegister src,
959 ConversionMode mode = RoundToZero, 955 VFPConversionMode mode = kDefaultRoundToZero,
960 const Condition cond = al); 956 const Condition cond = al);
961 void vcvt_s32_f64(const SwVfpRegister dst, 957 void vcvt_s32_f64(const SwVfpRegister dst,
962 const DwVfpRegister src, 958 const DwVfpRegister src,
963 ConversionMode mode = RoundToZero, 959 VFPConversionMode mode = kDefaultRoundToZero,
964 const Condition cond = al); 960 const Condition cond = al);
965 void vcvt_u32_f64(const SwVfpRegister dst, 961 void vcvt_u32_f64(const SwVfpRegister dst,
966 const DwVfpRegister src, 962 const DwVfpRegister src,
967 ConversionMode mode = RoundToZero, 963 VFPConversionMode mode = kDefaultRoundToZero,
968 const Condition cond = al); 964 const Condition cond = al);
969 void vcvt_f64_f32(const DwVfpRegister dst, 965 void vcvt_f64_f32(const DwVfpRegister dst,
970 const SwVfpRegister src, 966 const SwVfpRegister src,
971 ConversionMode mode = RoundToZero, 967 VFPConversionMode mode = kDefaultRoundToZero,
972 const Condition cond = al); 968 const Condition cond = al);
973 void vcvt_f32_f64(const SwVfpRegister dst, 969 void vcvt_f32_f64(const SwVfpRegister dst,
974 const DwVfpRegister src, 970 const DwVfpRegister src,
975 ConversionMode mode = RoundToZero, 971 VFPConversionMode mode = kDefaultRoundToZero,
976 const Condition cond = al); 972 const Condition cond = al);
977 973
978 void vabs(const DwVfpRegister dst, 974 void vabs(const DwVfpRegister dst,
979 const DwVfpRegister src, 975 const DwVfpRegister src,
980 const Condition cond = al); 976 const Condition cond = al);
981 void vadd(const DwVfpRegister dst, 977 void vadd(const DwVfpRegister dst,
982 const DwVfpRegister src1, 978 const DwVfpRegister src1,
983 const DwVfpRegister src2, 979 const DwVfpRegister src2,
984 const Condition cond = al); 980 const Condition cond = al);
985 void vsub(const DwVfpRegister dst, 981 void vsub(const DwVfpRegister dst,
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1263 public: 1259 public:
1264 explicit EnsureSpace(Assembler* assembler) { 1260 explicit EnsureSpace(Assembler* assembler) {
1265 assembler->CheckBuffer(); 1261 assembler->CheckBuffer();
1266 } 1262 }
1267 }; 1263 };
1268 1264
1269 1265
1270 } } // namespace v8::internal 1266 } } // namespace v8::internal
1271 1267
1272 #endif // V8_ARM_ASSEMBLER_ARM_H_ 1268 #endif // V8_ARM_ASSEMBLER_ARM_H_
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