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Issue 6366016: ARM: Add support for DoMathAbs with double inputs.... (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: Created 9 years, 11 months ago
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1 // Copyright 2010 the V8 project authors. All rights reserved. 1 // Copyright 2010 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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1057 if (instr->Bit(4) == 0) { 1057 if (instr->Bit(4) == 0) {
1058 if (instr->Opc1Value() == 0x7) { 1058 if (instr->Opc1Value() == 0x7) {
1059 // Other data processing instructions 1059 // Other data processing instructions
1060 if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x1)) { 1060 if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x1)) {
1061 // vmov register to register. 1061 // vmov register to register.
1062 if (instr->SzValue() == 0x1) { 1062 if (instr->SzValue() == 0x1) {
1063 Format(instr, "vmov.f64'cond 'Dd, 'Dm"); 1063 Format(instr, "vmov.f64'cond 'Dd, 'Dm");
1064 } else { 1064 } else {
1065 Format(instr, "vmov.f32'cond 'Sd, 'Sm"); 1065 Format(instr, "vmov.f32'cond 'Sd, 'Sm");
1066 } 1066 }
1067 } else if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x3)) {
1068 // vabs
1069 Format(instr, "vabs'cond 'Dd, 'Dm");
1067 } else if ((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)) { 1070 } else if ((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)) {
1068 DecodeVCVTBetweenDoubleAndSingle(instr); 1071 DecodeVCVTBetweenDoubleAndSingle(instr);
1069 } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) { 1072 } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) {
1070 DecodeVCVTBetweenFloatingPointAndInteger(instr); 1073 DecodeVCVTBetweenFloatingPointAndInteger(instr);
1071 } else if (((instr->Opc2Value() >> 1) == 0x6) && 1074 } else if (((instr->Opc2Value() >> 1) == 0x6) &&
1072 (instr->Opc3Value() & 0x1)) { 1075 (instr->Opc3Value() & 0x1)) {
1073 DecodeVCVTBetweenFloatingPointAndInteger(instr); 1076 DecodeVCVTBetweenFloatingPointAndInteger(instr);
1074 } else if (((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) && 1077 } else if (((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
1075 (instr->Opc3Value() & 0x1)) { 1078 (instr->Opc3Value() & 0x1)) {
1076 DecodeVCMP(instr); 1079 DecodeVCMP(instr);
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1427 pc += d.InstructionDecode(buffer, pc); 1430 pc += d.InstructionDecode(buffer, pc);
1428 fprintf(f, "%p %08x %s\n", 1431 fprintf(f, "%p %08x %s\n",
1429 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); 1432 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
1430 } 1433 }
1431 } 1434 }
1432 1435
1433 1436
1434 } // namespace disasm 1437 } // namespace disasm
1435 1438
1436 #endif // V8_TARGET_ARCH_ARM 1439 #endif // V8_TARGET_ARCH_ARM
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