ARM: Port new version of ParallelMove's GapResolver to ARM. Add MemOperand s...

src/arm/assembler-arm.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 575 matching lines @@
   // [rn +/- rm <shift_op> shift_imm]!     PreIndex/NegPreIndex
   // [rn], +/- rm <shift_op> shift_imm     PostIndex/NegPostIndex
   explicit MemOperand(Register rn, Register rm,
                       ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
 
   void set_offset(int32_t offset) {
       ASSERT(rm_.is(no_reg));
       offset_ = offset;
   }
 
-  uint32_t offset() {
+  uint32_t offset() const {
       ASSERT(rm_.is(no_reg));
       return offset_;
   }
 
   Register rn() const { return rn_; }
   Register rm() const { return rm_; }
 
+  bool OffsetIsEncodable() const {
+    return offset_ >= 0 ? is_uint12(offset_) : is_uint12(-offset_);
+  }
+
+  bool OffsetIsVFPEncodable() const {
+    return offset_ % 4 == 0 && offset_ < 1024 && offset_ > -1024;

[Søren Thygesen Gjesse, 2011/01/25 08:33:20]

is_unit8(offset_ >= 0 ? offset_ >> 2 : (-offset_) >> 2) instead of offset_ <
1024 && offset_ > -1024?

+  }
+
  private:
   Register rn_;  // base
   Register rm_;  // register offset
   int32_t offset_;  // valid if rm_ == no_reg
   ShiftOp shift_op_;
   int shift_imm_;  // valid if rm_ != no_reg && rs_ == no_reg
   AddrMode am_;  // bits P, U, and W
 
   friend class Assembler;
 };
@@ skipping 444 matching lines @@
   // Support for VFP.
   // All these APIs support S0 to S31 and D0 to D15.
   // Currently these APIs do not support extended D registers, i.e, D16 to D31.
   // However, some simple modifications can allow
   // these APIs to support D16 to D31.
 
   void vldr(const DwVfpRegister dst,
             const Register base,
             int offset,  // Offset must be a multiple of 4.
             const Condition cond = al);
+  void vldr(const DwVfpRegister dst,
+            const MemOperand& src,  // Source cannot be a FieldOperand.

[Søren Thygesen Gjesse, 2011/01/25 08:33:20]

I think the comments "Offset must be a multiple of 4" and "Source cannot be a
FieldOperand" should be removed and a comment added before all the vldr/vstr
functions saying that the offset must be a multiple of 4. FieldOperand is a
macro assembler function and should not be mentioned here. Maybe also mention
that if a MemOperand is used only addressing mode offset is aupported.

[William Hesse, 2011/01/25 17:25:13]

Comments are removed.  These functions now work with any offsets whatsoever.

On 2011/01/25 08:33:20, Søren Gjesse wrote:

+            const Condition cond = al);
 
   void vldr(const SwVfpRegister dst,
             const Register base,
             int offset,  // Offset must be a multiple of 4.
             const Condition cond = al);
+  void vldr(const SwVfpRegister dst,
+            const MemOperand& src,  // Source cannot be a FieldOperand.
+            const Condition cond = al);
 
   void vstr(const DwVfpRegister src,
             const Register base,
             int offset,  // Offset must be a multiple of 4.
             const Condition cond = al);
+  void vstr(const DwVfpRegister src,
+            const MemOperand& dst,  // Destination cannot be a FieldOperand.
+            const Condition cond = al);
 
   void vstr(const SwVfpRegister src,
             const Register base,
             int offset,  // Offset must be a multiple of 4.
             const Condition cond = al);
+  void vstr(const SwVfpRegister src,
+            const MemOperand& dst,  // Destination cannot be a FieldOperand.
+            const Condition cond = al);
 
   void vmov(const DwVfpRegister dst,
             double imm,
             const Condition cond = al);
   void vmov(const SwVfpRegister dst,
             const SwVfpRegister src,
             const Condition cond = al);
   void vmov(const DwVfpRegister dst,
             const DwVfpRegister src,
             const Condition cond = al);
@@ skipping 329 matching lines @@
  public:
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBuffer();
   }
 };
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_ARM_ASSEMBLER_ARM_H_