ARM: Merging constants in simulator and assembler header files and other clea...

src/arm/disasm-arm.cc

 // Copyright 2010 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 46 matching lines @@
 #include "v8.h"
 
 #if defined(V8_TARGET_ARCH_ARM)
 
 #include "constants-arm.h"
 #include "disasm.h"
 #include "macro-assembler.h"
 #include "platform.h"
 
 
-namespace assembler {
-namespace arm {
-
-namespace v8i = v8::internal;
+namespace v8 {
+namespace internal {
 
 
 //------------------------------------------------------------------------------
 
 // Decoder decodes and disassembles instructions into an output buffer.
 // It uses the converter to convert register names and call destinations into
 // more informative description.
 class Decoder {
  public:
   Decoder(const disasm::NameConverter& converter,
-          v8::internal::Vector<char> out_buffer)
+          Vector<char> out_buffer)
     : converter_(converter),
       out_buffer_(out_buffer),
       out_buffer_pos_(0) {
     out_buffer_[out_buffer_pos_] = '\0';
   }
 
   ~Decoder() {}
 
   // Writes one disassembled instruction into 'buffer' (0-terminated).
   // Returns the length of the disassembled machine instruction in bytes.
   int InstructionDecode(byte* instruction);
 
  private:
   // Bottleneck functions to print into the out_buffer.
   void PrintChar(const char ch);
   void Print(const char* str);
 
   // Printing of common values.
   void PrintRegister(int reg);
   void PrintSRegister(int reg);
   void PrintDRegister(int reg);
-  int FormatVFPRegister(Instr* instr, const char* format);
-  void PrintMovwMovt(Instr* instr);
-  int FormatVFPinstruction(Instr* instr, const char* format);
-  void PrintCondition(Instr* instr);
-  void PrintShiftRm(Instr* instr);
-  void PrintShiftImm(Instr* instr);
-  void PrintShiftSat(Instr* instr);
-  void PrintPU(Instr* instr);
+  int FormatVFPRegister(Instruction* instr, const char* format);
+  void PrintMovwMovt(Instruction* instr);
+  int FormatVFPinstruction(Instruction* instr, const char* format);
+  void PrintCondition(Instruction* instr);
+  void PrintShiftRm(Instruction* instr);
+  void PrintShiftImm(Instruction* instr);
+  void PrintShiftSat(Instruction* instr);
+  void PrintPU(Instruction* instr);
   void PrintSoftwareInterrupt(SoftwareInterruptCodes svc);
 
   // Handle formatting of instructions and their options.
-  int FormatRegister(Instr* instr, const char* option);
-  int FormatOption(Instr* instr, const char* option);
-  void Format(Instr* instr, const char* format);
-  void Unknown(Instr* instr);
+  int FormatRegister(Instruction* instr, const char* option);
+  int FormatOption(Instruction* instr, const char* option);
+  void Format(Instruction* instr, const char* format);
+  void Unknown(Instruction* instr);
 
   // Each of these functions decodes one particular instruction type, a 3-bit
   // field in the instruction encoding.
   // Types 0 and 1 are combined as they are largely the same except for the way
   // they interpret the shifter operand.
-  void DecodeType01(Instr* instr);
-  void DecodeType2(Instr* instr);
-  void DecodeType3(Instr* instr);
-  void DecodeType4(Instr* instr);
-  void DecodeType5(Instr* instr);
-  void DecodeType6(Instr* instr);
+  void DecodeType01(Instruction* instr);
+  void DecodeType2(Instruction* instr);
+  void DecodeType3(Instruction* instr);
+  void DecodeType4(Instruction* instr);
+  void DecodeType5(Instruction* instr);
+  void DecodeType6(Instruction* instr);
   // Type 7 includes special Debugger instructions.
-  int DecodeType7(Instr* instr);
+  int DecodeType7(Instruction* instr);
   // For VFP support.
-  void DecodeTypeVFP(Instr* instr);
-  void DecodeType6CoprocessorIns(Instr* instr);
+  void DecodeTypeVFP(Instruction* instr);
+  void DecodeType6CoprocessorIns(Instruction* instr);
 
-  void DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(Instr* instr);
-  void DecodeVCMP(Instr* instr);
-  void DecodeVCVTBetweenDoubleAndSingle(Instr* instr);
-  void DecodeVCVTBetweenFloatingPointAndInteger(Instr* instr);
+  void DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(Instruction* instr);
+  void DecodeVCMP(Instruction* instr);
+  void DecodeVCVTBetweenDoubleAndSingle(Instruction* instr);
+  void DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr);
 
   const disasm::NameConverter& converter_;
-  v8::internal::Vector<char> out_buffer_;
+  Vector<char> out_buffer_;
   int out_buffer_pos_;
 
   DISALLOW_COPY_AND_ASSIGN(Decoder);
 };
 
 
 // Support for assertions in the Decoder formatting functions.
 #define STRING_STARTS_WITH(string, compare_string) \
   (strncmp(string, compare_string, strlen(compare_string)) == 0)
 
@@ skipping 10 matching lines @@
   while (cur != '\0' && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
     PrintChar(cur);
     cur = *str++;
   }
   out_buffer_[out_buffer_pos_] = 0;
 }
 
 
 // These condition names are defined in a way to match the native disassembler
 // formatting. See for example the command "objdump -d <binary file>".
-static const char* cond_names[max_condition] = {
+static const char* cond_names[kNumberOfConditions] = {
   "eq", "ne", "cs" , "cc" , "mi" , "pl" , "vs" , "vc" ,
   "hi", "ls", "ge", "lt", "gt", "le", "", "invalid",
 };
 
 
 // Print the condition guarding the instruction.
-void Decoder::PrintCondition(Instr* instr) {
-  Print(cond_names[instr->ConditionField()]);
+void Decoder::PrintCondition(Instruction* instr) {
+  Print(cond_names[instr->ConditionValue()]);
 }
 
 
 // Print the register name according to the active name converter.
 void Decoder::PrintRegister(int reg) {
   Print(converter_.NameOfCPURegister(reg));
 }
 
 // Print the VFP S register name according to the active name converter.
 void Decoder::PrintSRegister(int reg) {
-  Print(assembler::arm::VFPRegisters::Name(reg, false));
+  Print(VFPRegisters::Name(reg, false));
 }
 
 // Print the  VFP D register name according to the active name converter.
 void Decoder::PrintDRegister(int reg) {
-  Print(assembler::arm::VFPRegisters::Name(reg, true));
+  Print(VFPRegisters::Name(reg, true));
 }
 
 
 // These shift names are defined in a way to match the native disassembler
 // formatting. See for example the command "objdump -d <binary file>".
-static const char* shift_names[max_shift] = {
+static const char* shift_names[kNumberOfShifts] = {
   "lsl", "lsr", "asr", "ror"
 };
 
 
 // Print the register shift operands for the instruction. Generally used for
 // data processing instructions.
-void Decoder::PrintShiftRm(Instr* instr) {
-  Shift shift = instr->ShiftField();
-  int shift_amount = instr->ShiftAmountField();
-  int rm = instr->RmField();
+void Decoder::PrintShiftRm(Instruction* instr) {
+  ShiftOp shift = instr->ShiftField();
+  int shift_index = instr->ShiftValue();
+  int shift_amount = instr->ShiftAmountValue();
+  int rm = instr->RmValue();
 
   PrintRegister(rm);
 
-  if ((instr->RegShiftField() == 0) && (shift == LSL) && (shift_amount == 0)) {
+  if ((instr->RegShiftValue() == 0) && (shift == LSL) && (shift_amount == 0)) {
     // Special case for using rm only.
     return;
   }
-  if (instr->RegShiftField() == 0) {
+  if (instr->RegShiftValue() == 0) {
     // by immediate
     if ((shift == ROR) && (shift_amount == 0)) {
       Print(", RRX");
       return;
     } else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) {
       shift_amount = 32;
     }
-    out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
-                                         ", %s #%d",
-                                         shift_names[shift], shift_amount);
+    out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                    ", %s #%d",
+                                    shift_names[shift_index],
+                                    shift_amount);
   } else {
     // by register
-    int rs = instr->RsField();
-    out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
-                                         ", %s ", shift_names[shift]);
+    int rs = instr->RsValue();
+    out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                    ", %s ", shift_names[shift_index]);
     PrintRegister(rs);
   }
 }
 
 
 // Print the immediate operand for the instruction. Generally used for data
 // processing instructions.
-void Decoder::PrintShiftImm(Instr* instr) {
-  int rotate = instr->RotateField() * 2;
-  int immed8 = instr->Immed8Field();
+void Decoder::PrintShiftImm(Instruction* instr) {
+  int rotate = instr->RotateValue() * 2;
+  int immed8 = instr->Immed8Value();
   int imm = (immed8 >> rotate) | (immed8 << (32 - rotate));
-  out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
-                                       "#%d", imm);
+  out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                  "#%d", imm);
 }
 
 
 // Print the optional shift and immediate used by saturating instructions.
-void Decoder::PrintShiftSat(Instr* instr) {
+void Decoder::PrintShiftSat(Instruction* instr) {
   int shift = instr->Bits(11, 7);
   if (shift > 0) {
-    out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
-                                         ", %s #%d",
-                                         shift_names[instr->Bit(6) * 2],
-                                         instr->Bits(11, 7));
+    out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                    ", %s #%d",
+                                    shift_names[instr->Bit(6) * 2],
+                                    instr->Bits(11, 7));
   }
 }
 
 
 // Print PU formatting to reduce complexity of FormatOption.
-void Decoder::PrintPU(Instr* instr) {
+void Decoder::PrintPU(Instruction* instr) {
   switch (instr->PUField()) {
-    case 0: {
+    case da_x: {
       Print("da");
       break;
     }
-    case 1: {
+    case ia_x: {
       Print("ia");
       break;
     }
-    case 2: {
+    case db_x: {
       Print("db");
       break;
     }
-    case 3: {
+    case ib_x: {
       Print("ib");
       break;
     }
     default: {
       UNREACHABLE();
       break;
     }
   }
 }
 
 
 // Print SoftwareInterrupt codes. Factoring this out reduces the complexity of
 // the FormatOption method.
 void Decoder::PrintSoftwareInterrupt(SoftwareInterruptCodes svc) {
   switch (svc) {
-    case call_rt_redirected:
-      Print("call_rt_redirected");
+    case kCallRtRedirected:
+      Print("call rt redirected");
       return;
-    case break_point:
-      Print("break_point");
+    case kBreakpoint:
+      Print("breakpoint");
       return;
     default:
-      if (svc >= stop) {
-        out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
-                                             "%d - 0x%x",
-                                             svc & kStopCodeMask,
-                                             svc & kStopCodeMask);
+      if (svc >= kStopCode) {
+        out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                        "%d - 0x%x",
+                                        svc & kStopCodeMask,
+                                        svc & kStopCodeMask);
       } else {
-        out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
-                                             "%d",
-                                             svc);
+        out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                        "%d",
+                                        svc);
       }
       return;
   }
 }
 
 
 // Handle all register based formatting in this function to reduce the
 // complexity of FormatOption.
-int Decoder::FormatRegister(Instr* instr, const char* format) {
+int Decoder::FormatRegister(Instruction* instr, const char* format) {
   ASSERT(format[0] == 'r');
   if (format[1] == 'n') {  // 'rn: Rn register
-    int reg = instr->RnField();
+    int reg = instr->RnValue();
     PrintRegister(reg);
     return 2;
   } else if (format[1] == 'd') {  // 'rd: Rd register
-    int reg = instr->RdField();
+    int reg = instr->RdValue();
     PrintRegister(reg);
     return 2;
   } else if (format[1] == 's') {  // 'rs: Rs register
-    int reg = instr->RsField();
+    int reg = instr->RsValue();
     PrintRegister(reg);
     return 2;
   } else if (format[1] == 'm') {  // 'rm: Rm register
-    int reg = instr->RmField();
+    int reg = instr->RmValue();
     PrintRegister(reg);
     return 2;
   } else if (format[1] == 't') {  // 'rt: Rt register
-    int reg = instr->RtField();
+    int reg = instr->RtValue();
     PrintRegister(reg);
     return 2;
   } else if (format[1] == 'l') {
     // 'rlist: register list for load and store multiple instructions
     ASSERT(STRING_STARTS_WITH(format, "rlist"));
-    int rlist = instr->RlistField();
+    int rlist = instr->RlistValue();
     int reg = 0;
     Print("{");
     // Print register list in ascending order, by scanning the bit mask.
     while (rlist != 0) {
       if ((rlist & 1) != 0) {
         PrintRegister(reg);
         if ((rlist >> 1) != 0) {
           Print(", ");
         }
       }
       reg++;
       rlist >>= 1;
     }
     Print("}");
     return 5;
   }
   UNREACHABLE();
   return -1;
 }
 
 
 // Handle all VFP register based formatting in this function to reduce the
 // complexity of FormatOption.
-int Decoder::FormatVFPRegister(Instr* instr, const char* format) {
+int Decoder::FormatVFPRegister(Instruction* instr, const char* format) {
   ASSERT((format[0] == 'S') || (format[0] == 'D'));
 
   if (format[1] == 'n') {
-    int reg = instr->VnField();
-    if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->NField()));
+    int reg = instr->VnValue();
+    if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->NValue()));
     if (format[0] == 'D') PrintDRegister(reg);
     return 2;
   } else if (format[1] == 'm') {
-    int reg = instr->VmField();
-    if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->MField()));
+    int reg = instr->VmValue();
+    if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->MValue()));
     if (format[0] == 'D') PrintDRegister(reg);
     return 2;
   } else if (format[1] == 'd') {
-    int reg = instr->VdField();
-    if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->DField()));
+    int reg = instr->VdValue();
+    if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->DValue()));
     if (format[0] == 'D') PrintDRegister(reg);
     return 2;
   }
 
   UNREACHABLE();
   return -1;
 }
 
 
-int Decoder::FormatVFPinstruction(Instr* instr, const char* format) {
+int Decoder::FormatVFPinstruction(Instruction* instr, const char* format) {
     Print(format);
     return 0;
 }
 
 
 // Print the movw or movt instruction.
-void Decoder::PrintMovwMovt(Instr* instr) {
-  int imm = instr->ImmedMovwMovtField();
-  int rd = instr->RdField();
+void Decoder::PrintMovwMovt(Instruction* instr) {
+  int imm = instr->ImmedMovwMovtValue();
+  int rd = instr->RdValue();
   PrintRegister(rd);
-  out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
-                                       ", #%d", imm);
+  out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                  ", #%d", imm);
 }
 
 
 // FormatOption takes a formatting string and interprets it based on
 // the current instructions. The format string points to the first
 // character of the option string (the option escape has already been
 // consumed by the caller.)  FormatOption returns the number of
 // characters that were consumed from the formatting string.
-int Decoder::FormatOption(Instr* instr, const char* format) {
+int Decoder::FormatOption(Instruction* instr, const char* format) {
   switch (format[0]) {
     case 'a': {  // 'a: accumulate multiplies
       if (instr->Bit(21) == 0) {
         Print("ul");
       } else {
         Print("la");
       }
       return 1;
     }
     case 'b': {  // 'b: byte loads or stores
       if (instr->HasB()) {
         Print("b");
       }
       return 1;
     }
     case 'c': {  // 'cond: conditional execution
       ASSERT(STRING_STARTS_WITH(format, "cond"));
       PrintCondition(instr);
       return 4;
     }
     case 'd': {  // 'd: vmov double immediate.
       double d = instr->DoubleImmedVmov();
-      out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
-                                           "#%g", d);
+      out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                      "#%g", d);
       return 1;
     }
     case 'f': {  // 'f: bitfield instructions - v7 and above.
       uint32_t lsbit = instr->Bits(11, 7);
       uint32_t width = instr->Bits(20, 16) + 1;
       if (instr->Bit(21) == 0) {
         // BFC/BFI:
         // Bits 20-16 represent most-significant bit. Covert to width.
         width -= lsbit;
         ASSERT(width > 0);
       }
       ASSERT((width + lsbit) <= 32);
-      out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
-                                           "#%d, #%d", lsbit, width);
+      out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                      "#%d, #%d", lsbit, width);
       return 1;
     }
     case 'h': {  // 'h: halfword operation for extra loads and stores
       if (instr->HasH()) {
         Print("h");
       } else {
         Print("b");
       }
       return 1;
     }
     case 'i': {  // 'i: immediate value from adjacent bits.
       // Expects tokens in the form imm%02d@%02d, ie. imm05@07, imm10@16
       int width = (format[3] - '0') * 10 + (format[4] - '0');
       int lsb   = (format[6] - '0') * 10 + (format[7] - '0');
 
       ASSERT((width >= 1) && (width <= 32));
       ASSERT((lsb >= 0) && (lsb <= 31));
       ASSERT((width + lsb) <= 32);
 
-      out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
-                                           "%d",
-                                           instr->Bits(width + lsb - 1, lsb));
+      out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                      "%d",
+                                      instr->Bits(width + lsb - 1, lsb));
       return 8;
     }
     case 'l': {  // 'l: branch and link
       if (instr->HasLink()) {
         Print("l");
       }
       return 1;
     }
     case 'm': {
       if (format[1] == 'w') {
@@ skipping 13 matching lines @@
           }
         } else {
           Print("str");
         }
         return 5;
       }
       // 'msg: for simulator break instructions
       ASSERT(STRING_STARTS_WITH(format, "msg"));
       byte* str =
           reinterpret_cast<byte*>(instr->InstructionBits() & 0x0fffffff);
-      out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
-                                           "%s", converter_.NameInCode(str));
+      out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                      "%s", converter_.NameInCode(str));
       return 3;
     }
     case 'o': {
       if ((format[3] == '1') && (format[4] == '2')) {
         // 'off12: 12-bit offset for load and store instructions
         ASSERT(STRING_STARTS_WITH(format, "off12"));
-        out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
-                                             "%d", instr->Offset12Field());
+        out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                        "%d", instr->Offset12Value());
         return 5;
       } else if (format[3] == '0') {
         // 'off0to3and8to19 16-bit immediate encoded in bits 19-8 and 3-0.
         ASSERT(STRING_STARTS_WITH(format, "off0to3and8to19"));
-        out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
-                                            "%d",
-                                            (instr->Bits(19, 8) << 4) +
-                                                instr->Bits(3, 0));
+        out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                        "%d",
+                                        (instr->Bits(19, 8) << 4) +
+                                        instr->Bits(3, 0));
         return 15;
       }
       // 'off8: 8-bit offset for extra load and store instructions
       ASSERT(STRING_STARTS_WITH(format, "off8"));
-      int offs8 = (instr->ImmedHField() << 4) | instr->ImmedLField();
-      out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
-                                           "%d", offs8);
+      int offs8 = (instr->ImmedHValue() << 4) | instr->ImmedLValue();
+      out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                      "%d", offs8);
       return 4;
     }
     case 'p': {  // 'pu: P and U bits for load and store instructions
       ASSERT(STRING_STARTS_WITH(format, "pu"));
       PrintPU(instr);
       return 2;
     }
     case 'r': {
       return FormatRegister(instr, format);
     }
     case 's': {
       if (format[1] == 'h') {  // 'shift_op or 'shift_rm or 'shift_sat.
         if (format[6] == 'o') {  // 'shift_op
           ASSERT(STRING_STARTS_WITH(format, "shift_op"));
-          if (instr->TypeField() == 0) {
+          if (instr->TypeValue() == 0) {
             PrintShiftRm(instr);
           } else {
-            ASSERT(instr->TypeField() == 1);
+            ASSERT(instr->TypeValue() == 1);
             PrintShiftImm(instr);
           }
           return 8;
         } else if (format[6] == 's') {  // 'shift_sat.
           ASSERT(STRING_STARTS_WITH(format, "shift_sat"));
           PrintShiftSat(instr);
           return 9;
         } else {  // 'shift_rm
           ASSERT(STRING_STARTS_WITH(format, "shift_rm"));
           PrintShiftRm(instr);
           return 8;
         }
       } else if (format[1] == 'v') {  // 'svc
         ASSERT(STRING_STARTS_WITH(format, "svc"));
-        PrintSoftwareInterrupt(instr->SvcField());
+        PrintSoftwareInterrupt(instr->SvcValue());
         return 3;
       } else if (format[1] == 'i') {  // 'sign: signed extra loads and stores
         ASSERT(STRING_STARTS_WITH(format, "sign"));
         if (instr->HasSign()) {
           Print("s");
         }
         return 4;
       }
       // 's: S field of data processing instructions
       if (instr->HasS()) {
         Print("s");
       }
       return 1;
     }
     case 't': {  // 'target: target of branch instructions
       ASSERT(STRING_STARTS_WITH(format, "target"));
-      int off = (instr->SImmed24Field() << 2) + 8;
-      out_buffer_pos_ += v8i::OS::SNPrintF(
-          out_buffer_ + out_buffer_pos_,
-          "%+d -> %s",
-          off,
-          converter_.NameOfAddress(reinterpret_cast<byte*>(instr) + off));
+      int off = (instr->SImmed24Value() << 2) + 8;
+      out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                      "%+d -> %s",
+                                      off,
+                                      converter_.NameOfAddress(
+                                        reinterpret_cast<byte*>(instr) + off));
       return 6;
     }
     case 'u': {  // 'u: signed or unsigned multiplies
       // The manual gets the meaning of bit 22 backwards in the multiply
       // instruction overview on page A3.16.2.  The instructions that
       // exist in u and s variants are the following:
       // smull A4.1.87
       // umull A4.1.129
       // umlal A4.1.128
       // smlal A4.1.76
@@ skipping 28 matching lines @@
     }
   }
   UNREACHABLE();
   return -1;
 }
 
 
 // Format takes a formatting string for a whole instruction and prints it into
 // the output buffer. All escaped options are handed to FormatOption to be
 // parsed further.
-void Decoder::Format(Instr* instr, const char* format) {
+void Decoder::Format(Instruction* instr, const char* format) {
   char cur = *format++;
   while ((cur != 0) && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
     if (cur == '\'') {  // Single quote is used as the formatting escape.
       format += FormatOption(instr, format);
     } else {
       out_buffer_[out_buffer_pos_++] = cur;
     }
     cur = *format++;
   }
   out_buffer_[out_buffer_pos_]  = '\0';
 }
 
 
 // For currently unimplemented decodings the disassembler calls Unknown(instr)
 // which will just print "unknown" of the instruction bits.
-void Decoder::Unknown(Instr* instr) {
+void Decoder::Unknown(Instruction* instr) {
   Format(instr, "unknown");
 }
 
 
-void Decoder::DecodeType01(Instr* instr) {
-  int type = instr->TypeField();
+void Decoder::DecodeType01(Instruction* instr) {
+  int type = instr->TypeValue();
   if ((type == 0) && instr->IsSpecialType0()) {
     // multiply instruction or extra loads and stores
     if (instr->Bits(7, 4) == 9) {
       if (instr->Bit(24) == 0) {
         // multiply instructions
         if (instr->Bit(23) == 0) {
           if (instr->Bit(21) == 0) {
             // The MUL instruction description (A 4.1.33) refers to Rd as being
             // the destination for the operation, but it confusingly uses the
             // Rn field to encode it.
@@ skipping 13 matching lines @@
           // RdHi == Rn field
           // The order of registers is: <RdLo>, <RdHi>, <Rm>, <Rs>
           Format(instr, "'um'al'cond's 'rd, 'rn, 'rm, 'rs");
         }
       } else {
         Unknown(instr);  // not used by V8
       }
     } else if ((instr->Bit(20) == 0) && ((instr->Bits(7, 4) & 0xd) == 0xd)) {
       // ldrd, strd
       switch (instr->PUField()) {
-        case 0: {
+        case da_x: {
           if (instr->Bit(22) == 0) {
             Format(instr, "'memop'cond's 'rd, ['rn], -'rm");
           } else {
             Format(instr, "'memop'cond's 'rd, ['rn], #-'off8");
           }
           break;
         }
-        case 1: {
+        case ia_x: {
           if (instr->Bit(22) == 0) {
             Format(instr, "'memop'cond's 'rd, ['rn], +'rm");
           } else {
             Format(instr, "'memop'cond's 'rd, ['rn], #+'off8");
           }
           break;
         }
-        case 2: {
+        case db_x: {
           if (instr->Bit(22) == 0) {
             Format(instr, "'memop'cond's 'rd, ['rn, -'rm]'w");
           } else {
             Format(instr, "'memop'cond's 'rd, ['rn, #-'off8]'w");
           }
           break;
         }
-        case 3: {
+        case ib_x: {
           if (instr->Bit(22) == 0) {
             Format(instr, "'memop'cond's 'rd, ['rn, +'rm]'w");
           } else {
             Format(instr, "'memop'cond's 'rd, ['rn, #+'off8]'w");
           }
           break;
         }
         default: {
           // The PU field is a 2-bit field.
           UNREACHABLE();
           break;
         }
       }
     } else {
       // extra load/store instructions
       switch (instr->PUField()) {
-        case 0: {
+        case da_x: {
           if (instr->Bit(22) == 0) {
             Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
           } else {
             Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8");
           }
           break;
         }
-        case 1: {
+        case ia_x: {
           if (instr->Bit(22) == 0) {
             Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
           } else {
             Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8");
           }
           break;
         }
-        case 2: {
+        case db_x: {
           if (instr->Bit(22) == 0) {
             Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
           } else {
             Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w");
           }
           break;
         }
-        case 3: {
+        case ib_x: {
           if (instr->Bit(22) == 0) {
             Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
           } else {
             Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w");
           }
           break;
         }
         default: {
           // The PU field is a 2-bit field.
           UNREACHABLE();
           break;
         }
       }
       return;
     }
   } else if ((type == 0) && instr->IsMiscType0()) {
     if (instr->Bits(22, 21) == 1) {
-      switch (instr->Bits(7, 4)) {
+      switch (instr->BitField(7, 4)) {
         case BX:
           Format(instr, "bx'cond 'rm");
           break;
         case BLX:
           Format(instr, "blx'cond 'rm");
           break;
         case BKPT:
           Format(instr, "bkpt 'off0to3and8to19");
           break;
         default:
           Unknown(instr);  // not used by V8
           break;
       }
     } else if (instr->Bits(22, 21) == 3) {
-      switch (instr->Bits(7, 4)) {
+      switch (instr->BitField(7, 4)) {
         case CLZ:
           Format(instr, "clz'cond 'rd, 'rm");
           break;
         default:
           Unknown(instr);  // not used by V8
           break;
       }
     } else {
       Unknown(instr);  // not used by V8
     }
@@ skipping 86 matching lines @@
       default: {
         // The Opcode field is a 4-bit field.
         UNREACHABLE();
         break;
       }
     }
   }
 }
 
 
-void Decoder::DecodeType2(Instr* instr) {
+void Decoder::DecodeType2(Instruction* instr) {
   switch (instr->PUField()) {
-    case 0: {
+    case da_x: {
       if (instr->HasW()) {
         Unknown(instr);  // not used in V8
       }
       Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
       break;
     }
-    case 1: {
+    case ia_x: {
       if (instr->HasW()) {
         Unknown(instr);  // not used in V8
       }
       Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
       break;
     }
-    case 2: {
+    case db_x: {
       Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
       break;
     }
-    case 3: {
+    case ib_x: {
       Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
       break;
     }
     default: {
       // The PU field is a 2-bit field.
       UNREACHABLE();
       break;
     }
   }
 }
 
 
-void Decoder::DecodeType3(Instr* instr) {
+void Decoder::DecodeType3(Instruction* instr) {
   switch (instr->PUField()) {
-    case 0: {
+    case da_x: {
       ASSERT(!instr->HasW());
       Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
       break;
     }
-    case 1: {
+    case ia_x: {
       if (instr->HasW()) {
         ASSERT(instr->Bits(5, 4) == 0x1);
         if (instr->Bit(22) == 0x1) {
           Format(instr, "usat 'rd, #'imm05@16, 'rm'shift_sat");
         } else {
           UNREACHABLE();  // SSAT.
         }
       } else {
         Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
       }
       break;
     }
-    case 2: {
+    case db_x: {
       Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
       break;
     }
-    case 3: {
+    case ib_x: {
       if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) {
         uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16));
         uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
         uint32_t msbit = widthminus1 + lsbit;
         if (msbit <= 31) {
           if (instr->Bit(22)) {
             Format(instr, "ubfx'cond 'rd, 'rm, 'f");
           } else {
             Format(instr, "sbfx'cond 'rd, 'rm, 'f");
           }
         } else {
           UNREACHABLE();
         }
       } else if (!instr->HasW() && (instr->Bits(6, 4) == 0x1)) {
         uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
         uint32_t msbit = static_cast<uint32_t>(instr->Bits(20, 16));
         if (msbit >= lsbit) {
-          if (instr->RmField() == 15) {
+          if (instr->RmValue() == 15) {
             Format(instr, "bfc'cond 'rd, 'f");
           } else {
             Format(instr, "bfi'cond 'rd, 'rm, 'f");
           }
         } else {
           UNREACHABLE();
         }
       } else {
         Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
       }
       break;
     }
     default: {
       // The PU field is a 2-bit field.
       UNREACHABLE();
       break;
     }
   }
 }
 
 
-void Decoder::DecodeType4(Instr* instr) {
+void Decoder::DecodeType4(Instruction* instr) {
   ASSERT(instr->Bit(22) == 0);  // Privileged mode currently not supported.
   if (instr->HasL()) {
     Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
   } else {
     Format(instr, "stm'cond'pu 'rn'w, 'rlist");
   }
 }
 
 
-void Decoder::DecodeType5(Instr* instr) {
+void Decoder::DecodeType5(Instruction* instr) {
   Format(instr, "b'l'cond 'target");
 }
 
 
-void Decoder::DecodeType6(Instr* instr) {
+void Decoder::DecodeType6(Instruction* instr) {
   DecodeType6CoprocessorIns(instr);
 }
 
 
-int Decoder::DecodeType7(Instr* instr) {
+int Decoder::DecodeType7(Instruction* instr) {
   if (instr->Bit(24) == 1) {
-    if (instr->SvcField() >= stop) {
+    if (instr->SvcValue() >= kStopCode) {
       Format(instr, "stop'cond 'svc");
       // Also print the stop message. Its address is encoded
       // in the following 4 bytes.
-      out_buffer_pos_ +=
-        v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
-                          "\n  %p  %08x       stop message: %s",
-                          reinterpret_cast<int32_t*>(instr + Instr::kInstrSize),
-                          *reinterpret_cast<char**>(instr + Instr::kInstrSize),
-                          *reinterpret_cast<char**>(instr + Instr::kInstrSize));
-      // We have decoded 2 * Instr::kInstrSize bytes.
-      return 2 * Instr::kInstrSize;
+      out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                      "\n  %p  %08x       stop message: %s",
+                                      reinterpret_cast<int32_t*>(instr
+                                                     + Instruction::kInstrSize),
+                                      *reinterpret_cast<char**>(instr
+                                                    + Instruction::kInstrSize),
+                                      *reinterpret_cast<char**>(instr
+                                                    + Instruction::kInstrSize));
+      // We have decoded 2 * Instruction::kInstrSize bytes.
+      return 2 * Instruction::kInstrSize;
     } else {
       Format(instr, "svc'cond 'svc");
     }
   } else {
     DecodeTypeVFP(instr);
   }
-  return Instr::kInstrSize;
+  return Instruction::kInstrSize;
 }
 
 
-// void Decoder::DecodeTypeVFP(Instr* instr)
+// void Decoder::DecodeTypeVFP(Instruction* instr)
 // vmov: Sn = Rt
 // vmov: Rt = Sn
 // vcvt: Dd = Sm
 // vcvt: Sd = Dm
 // Dd = vadd(Dn, Dm)
 // Dd = vsub(Dn, Dm)
 // Dd = vmul(Dn, Dm)
 // Dd = vdiv(Dn, Dm)
 // vcmp(Dd, Dm)
 // vmrs
 // vmsr
 // Dd = vsqrt(Dm)
-void Decoder::DecodeTypeVFP(Instr* instr) {
-  ASSERT((instr->TypeField() == 7) && (instr->Bit(24) == 0x0) );
+void Decoder::DecodeTypeVFP(Instruction* instr) {
+  ASSERT((instr->TypeValue() == 7) && (instr->Bit(24) == 0x0) );
   ASSERT(instr->Bits(11, 9) == 0x5);
 
   if (instr->Bit(4) == 0) {
-    if (instr->Opc1Field() == 0x7) {
+    if (instr->Opc1Value() == 0x7) {
       // Other data processing instructions
-      if ((instr->Opc2Field() == 0x0) && (instr->Opc3Field() == 0x1)) {
+      if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x1)) {
         // vmov register to register.
-        if (instr->SzField() == 0x1) {
+        if (instr->SzValue() == 0x1) {
           Format(instr, "vmov.f64'cond 'Dd, 'Dm");
         } else {
           Format(instr, "vmov.f32'cond 'Sd, 'Sm");
         }
-      } else if ((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3)) {
+      } else if ((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)) {
         DecodeVCVTBetweenDoubleAndSingle(instr);
-      } else if ((instr->Opc2Field() == 0x8) && (instr->Opc3Field() & 0x1)) {
+      } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) {
         DecodeVCVTBetweenFloatingPointAndInteger(instr);
-      } else if (((instr->Opc2Field() >> 1) == 0x6) &&
-                 (instr->Opc3Field() & 0x1)) {
+      } else if (((instr->Opc2Value() >> 1) == 0x6) &&
+                 (instr->Opc3Value() & 0x1)) {
         DecodeVCVTBetweenFloatingPointAndInteger(instr);
-      } else if (((instr->Opc2Field() == 0x4) || (instr->Opc2Field() == 0x5)) &&
-                 (instr->Opc3Field() & 0x1)) {
+      } else if (((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
+                 (instr->Opc3Value() & 0x1)) {
         DecodeVCMP(instr);
-      } else if (((instr->Opc2Field() == 0x1)) && (instr->Opc3Field() == 0x3)) {
+      } else if (((instr->Opc2Value() == 0x1)) && (instr->Opc3Value() == 0x3)) {
         Format(instr, "vsqrt.f64'cond 'Dd, 'Dm");
-      } else if (instr->Opc3Field() == 0x0) {
-        if (instr->SzField() == 0x1) {
+      } else if (instr->Opc3Value() == 0x0) {
+        if (instr->SzValue() == 0x1) {
           Format(instr, "vmov.f64'cond 'Dd, 'd");
         } else {
           Unknown(instr);  // Not used by V8.
         }
       } else {
         Unknown(instr);  // Not used by V8.
       }
-    } else if (instr->Opc1Field() == 0x3) {
-      if (instr->SzField() == 0x1) {
-        if (instr->Opc3Field() & 0x1) {
+    } else if (instr->Opc1Value() == 0x3) {
+      if (instr->SzValue() == 0x1) {
+        if (instr->Opc3Value() & 0x1) {
           Format(instr, "vsub.f64'cond 'Dd, 'Dn, 'Dm");
         } else {
           Format(instr, "vadd.f64'cond 'Dd, 'Dn, 'Dm");
         }
       } else {
         Unknown(instr);  // Not used by V8.
       }
-    } else if ((instr->Opc1Field() == 0x2) && !(instr->Opc3Field() & 0x1)) {
-      if (instr->SzField() == 0x1) {
+    } else if ((instr->Opc1Value() == 0x2) && !(instr->Opc3Value() & 0x1)) {
+      if (instr->SzValue() == 0x1) {
         Format(instr, "vmul.f64'cond 'Dd, 'Dn, 'Dm");
       } else {
         Unknown(instr);  // Not used by V8.
       }
-    } else if ((instr->Opc1Field() == 0x4) && !(instr->Opc3Field() & 0x1)) {
-      if (instr->SzField() == 0x1) {
+    } else if ((instr->Opc1Value() == 0x4) && !(instr->Opc3Value() & 0x1)) {
+      if (instr->SzValue() == 0x1) {
         Format(instr, "vdiv.f64'cond 'Dd, 'Dn, 'Dm");
       } else {
         Unknown(instr);  // Not used by V8.
       }
     } else {
       Unknown(instr);  // Not used by V8.
     }
   } else {
-    if ((instr->VCField() == 0x0) &&
-        (instr->VAField() == 0x0)) {
+    if ((instr->VCValue() == 0x0) &&
+        (instr->VAValue() == 0x0)) {
       DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(instr);
-    } else if ((instr->VCField() == 0x0) &&
-               (instr->VAField() == 0x7) &&
+    } else if ((instr->VCValue() == 0x0) &&
+               (instr->VAValue() == 0x7) &&
                (instr->Bits(19, 16) == 0x1)) {
-      if (instr->VLField() == 0) {
+      if (instr->VLValue() == 0) {
         if (instr->Bits(15, 12) == 0xF) {
           Format(instr, "vmsr'cond FPSCR, APSR");
         } else {
           Format(instr, "vmsr'cond FPSCR, 'rt");
         }
       } else {
         if (instr->Bits(15, 12) == 0xF) {
           Format(instr, "vmrs'cond APSR, FPSCR");
         } else {
           Format(instr, "vmrs'cond 'rt, FPSCR");
         }
       }
     }
   }
 }
 
 
-void Decoder::DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(Instr* instr) {
-  ASSERT((instr->Bit(4) == 1) && (instr->VCField() == 0x0) &&
-         (instr->VAField() == 0x0));
+void Decoder::DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(
+    Instruction* instr) {
+  ASSERT((instr->Bit(4) == 1) && (instr->VCValue() == 0x0) &&
+         (instr->VAValue() == 0x0));
 
-  bool to_arm_register = (instr->VLField() == 0x1);
+  bool to_arm_register = (instr->VLValue() == 0x1);
 
   if (to_arm_register) {
     Format(instr, "vmov'cond 'rt, 'Sn");
   } else {
     Format(instr, "vmov'cond 'Sn, 'rt");
   }
 }
 
 
-void Decoder::DecodeVCMP(Instr* instr) {
-  ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7));
-  ASSERT(((instr->Opc2Field() == 0x4) || (instr->Opc2Field() == 0x5)) &&
-         (instr->Opc3Field() & 0x1));
+void Decoder::DecodeVCMP(Instruction* instr) {
+  ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
+  ASSERT(((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
+         (instr->Opc3Value() & 0x1));
 
   // Comparison.
-  bool dp_operation = (instr->SzField() == 1);
+  bool dp_operation = (instr->SzValue() == 1);
   bool raise_exception_for_qnan = (instr->Bit(7) == 0x1);
 
   if (dp_operation && !raise_exception_for_qnan) {
-    if (instr->Opc2Field() == 0x4) {
+    if (instr->Opc2Value() == 0x4) {
       Format(instr, "vcmp.f64'cond 'Dd, 'Dm");
-    } else if (instr->Opc2Field() == 0x5) {
+    } else if (instr->Opc2Value() == 0x5) {
       Format(instr, "vcmp.f64'cond 'Dd, #0.0");
     } else {
       Unknown(instr);  // invalid
     }
   } else {
     Unknown(instr);  // Not used by V8.
   }
 }
 
 
-void Decoder::DecodeVCVTBetweenDoubleAndSingle(Instr* instr) {
-  ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7));
-  ASSERT((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3));
+void Decoder::DecodeVCVTBetweenDoubleAndSingle(Instruction* instr) {
+  ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
+  ASSERT((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3));
 
-  bool double_to_single = (instr->SzField() == 1);
+  bool double_to_single = (instr->SzValue() == 1);
 
   if (double_to_single) {
     Format(instr, "vcvt.f32.f64'cond 'Sd, 'Dm");
   } else {
     Format(instr, "vcvt.f64.f32'cond 'Dd, 'Sm");
   }
 }
 
 
-void Decoder::DecodeVCVTBetweenFloatingPointAndInteger(Instr* instr) {
-  ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7));
-  ASSERT(((instr->Opc2Field() == 0x8) && (instr->Opc3Field() & 0x1)) ||
-         (((instr->Opc2Field() >> 1) == 0x6) && (instr->Opc3Field() & 0x1)));
+void Decoder::DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr) {
+  ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
+  ASSERT(((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) ||
+         (((instr->Opc2Value() >> 1) == 0x6) && (instr->Opc3Value() & 0x1)));
 
   bool to_integer = (instr->Bit(18) == 1);
-  bool dp_operation = (instr->SzField() == 1);
+  bool dp_operation = (instr->SzValue() == 1);
   if (to_integer) {
     bool unsigned_integer = (instr->Bit(16) == 0);
 
     if (dp_operation) {
       if (unsigned_integer) {
         Format(instr, "vcvt.u32.f64'cond 'Sd, 'Dm");
       } else {
         Format(instr, "vcvt.s32.f64'cond 'Sd, 'Dm");
       }
     } else {
@@ skipping 21 matching lines @@
     }
   }
 }
 
 
 // Decode Type 6 coprocessor instructions.
 // Dm = vmov(Rt, Rt2)
 // <Rt, Rt2> = vmov(Dm)
 // Ddst = MEM(Rbase + 4*offset).
 // MEM(Rbase + 4*offset) = Dsrc.
-void Decoder::DecodeType6CoprocessorIns(Instr* instr) {
-  ASSERT((instr->TypeField() == 6));
+void Decoder::DecodeType6CoprocessorIns(Instruction* instr) {
+  ASSERT(instr->TypeValue() == 6);
 
-  if (instr->CoprocessorField() == 0xA) {
-    switch (instr->OpcodeField()) {
+  if (instr->CoprocessorValue() == 0xA) {
+    switch (instr->OpcodeValue()) {
       case 0x8:
       case 0xA:
         if (instr->HasL()) {
           Format(instr, "vldr'cond 'Sd, ['rn - 4*'imm08@00]");
         } else {
           Format(instr, "vstr'cond 'Sd, ['rn - 4*'imm08@00]");
         }
         break;
       case 0xC:
       case 0xE:
         if (instr->HasL()) {
           Format(instr, "vldr'cond 'Sd, ['rn + 4*'imm08@00]");
         } else {
           Format(instr, "vstr'cond 'Sd, ['rn + 4*'imm08@00]");
         }
         break;
       default:
         Unknown(instr);  // Not used by V8.
         break;
     }
-  } else if (instr->CoprocessorField() == 0xB) {
-    switch (instr->OpcodeField()) {
+  } else if (instr->CoprocessorValue() == 0xB) {
+    switch (instr->OpcodeValue()) {
       case 0x2:
         // Load and store double to two GP registers
         if (instr->Bits(7, 4) != 0x1) {
           Unknown(instr);  // Not used by V8.
         } else if (instr->HasL()) {
           Format(instr, "vmov'cond 'rt, 'rn, 'Dm");
         } else {
           Format(instr, "vmov'cond 'Dm, 'rt, 'rn");
         }
         break;
@@ skipping 16 matching lines @@
         break;
     }
   } else {
     UNIMPLEMENTED();  // Not used by V8.
   }
 }
 
 
 // Disassemble the instruction at *instr_ptr into the output buffer.
 int Decoder::InstructionDecode(byte* instr_ptr) {
-  Instr* instr = Instr::At(instr_ptr);
+  Instruction* instr = Instruction::At(instr_ptr);
   // Print raw instruction bytes.
-  out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_,
-                                       "%08x       ",
-                                       instr->InstructionBits());
-  if (instr->ConditionField() == special_condition) {
+  out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                                  "%08x       ",
+                                  instr->InstructionBits());
+  if (instr->ConditionField() == kSpecialCondition) {
     UNIMPLEMENTED();
-    return Instr::kInstrSize;
+    return Instruction::kInstrSize;
   }
-  switch (instr->TypeField()) {
+  switch (instr->TypeValue()) {
     case 0:
     case 1: {
       DecodeType01(instr);
       break;
     }
     case 2: {
       DecodeType2(instr);
       break;
     }
     case 3: {
@@ skipping 14 matching lines @@
     }
     case 7: {
       return DecodeType7(instr);
     }
     default: {
       // The type field is 3-bits in the ARM encoding.
       UNREACHABLE();
       break;
     }
   }
-  return Instr::kInstrSize;
+  return Instruction::kInstrSize;
 }
 
 
-} }  // namespace assembler::arm
+} }  // namespace v8::internal
 
 
 
 //------------------------------------------------------------------------------
 
 namespace disasm {
 
-namespace v8i = v8::internal;
-
 
 const char* NameConverter::NameOfAddress(byte* addr) const {
   static v8::internal::EmbeddedVector<char, 32> tmp_buffer;
   v8::internal::OS::SNPrintF(tmp_buffer, "%p", addr);
   return tmp_buffer.start();
 }
 
 
 const char* NameConverter::NameOfConstant(byte* addr) const {
   return NameOfAddress(addr);
 }
 
 
 const char* NameConverter::NameOfCPURegister(int reg) const {
-  return assembler::arm::Registers::Name(reg);
+  return v8::internal::Registers::Name(reg);
 }
 
 
 const char* NameConverter::NameOfByteCPURegister(int reg) const {
   UNREACHABLE();  // ARM does not have the concept of a byte register
   return "nobytereg";
 }
 
 
 const char* NameConverter::NameOfXMMRegister(int reg) const {
@@ skipping 13 matching lines @@
 
 Disassembler::Disassembler(const NameConverter& converter)
     : converter_(converter) {}
 
 
 Disassembler::~Disassembler() {}
 
 
 int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
                                     byte* instruction) {
-  assembler::arm::Decoder d(converter_, buffer);
+  v8::internal::Decoder d(converter_, buffer);
   return d.InstructionDecode(instruction);
 }
 
 
 int Disassembler::ConstantPoolSizeAt(byte* instruction) {
   int instruction_bits = *(reinterpret_cast<int*>(instruction));
   if ((instruction_bits & 0xfff00000) == 0x03000000) {
     return instruction_bits & 0x0000ffff;
   } else {
     return -1;
@@ skipping 11 matching lines @@
     pc += d.InstructionDecode(buffer, pc);
     fprintf(f, "%p    %08x      %s\n",
             prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_ARM