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Issue 6142004: ARM: Fix comparison of NaN values.... (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: '' Created 9 years, 11 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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2333 emit(cond | 0xE*B24 | B23 | src1.code()*B16 | 2333 emit(cond | 0xE*B24 | B23 | src1.code()*B16 |
2334 dst.code()*B12 | 0x5*B9 | B8 | src2.code()); 2334 dst.code()*B12 | 0x5*B9 | B8 | src2.code());
2335 } 2335 }
2336 2336
2337 2337
2338 void Assembler::vcmp(const DwVfpRegister src1, 2338 void Assembler::vcmp(const DwVfpRegister src1,
2339 const DwVfpRegister src2, 2339 const DwVfpRegister src2,
2340 const SBit s, 2340 const SBit s,
2341 const Condition cond) { 2341 const Condition cond) {
2342 // vcmp(Dd, Dm) double precision floating point comparison. 2342 // vcmp(Dd, Dm) double precision floating point comparison.
2343 // We set bit E, as we want any NaN to set the cumulative exception flag
2344 // in the FPSCR.
2343 // Instruction details available in ARM DDI 0406A, A8-570. 2345 // Instruction details available in ARM DDI 0406A, A8-570.
2344 // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0100 (19-16) | 2346 // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0100 (19-16) |
2345 // Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=? | 1(6) | M(5)=? | 0(4) | Vm(3-0) 2347 // Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=1 | 1(6) | M(5)=? | 0(4) | Vm(3-0)
2346 ASSERT(CpuFeatures::IsEnabled(VFP3)); 2348 ASSERT(CpuFeatures::IsEnabled(VFP3));
2347 emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 | 2349 emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 |
2348 src1.code()*B12 | 0x5*B9 | B8 | B6 | src2.code()); 2350 src1.code()*B12 | 0x5*B9 | B8 | B7 | B6 | src2.code());
2349 } 2351 }
2350 2352
2351 2353
2352 void Assembler::vcmp(const DwVfpRegister src1, 2354 void Assembler::vcmp(const DwVfpRegister src1,
2353 const double src2, 2355 const double src2,
2354 const SBit s, 2356 const SBit s,
2355 const Condition cond) { 2357 const Condition cond) {
2356 // vcmp(Dd, Dm) double precision floating point comparison. 2358 // vcmp(Dd, Dm) double precision floating point comparison.
2357 // Instruction details available in ARM DDI 0406A, A8-570. 2359 // Instruction details available in ARM DDI 0406A, A8-570.
2360 // We set bit E, as we want any NaN to set the cumulative exception flag
2361 // in the FPSCR.
2358 // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0101 (19-16) | 2362 // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0101 (19-16) |
2359 // Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=? | 1(6) | M(5)=? | 0(4) | 0000(3-0) 2363 // Vd(15-12) | 101(11-9) | sz(8)=1 | E(7)=1 | 1(6) | M(5)=? | 0(4) | 0000(3-0)
2360 ASSERT(CpuFeatures::IsEnabled(VFP3)); 2364 ASSERT(CpuFeatures::IsEnabled(VFP3));
2361 ASSERT(src2 == 0.0); 2365 ASSERT(src2 == 0.0);
2362 emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 | B16 | 2366 emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 | B16 |
2363 src1.code()*B12 | 0x5*B9 | B8 | B6); 2367 src1.code()*B12 | 0x5*B9 | B8 | B7 | B6);
2364 } 2368 }
2365 2369
2366 2370
2367 void Assembler::vmsr(Register dst, Condition cond) { 2371 void Assembler::vmsr(Register dst, Condition cond) {
2368 // Instruction details available in ARM DDI 0406A, A8-652. 2372 // Instruction details available in ARM DDI 0406A, A8-652.
2369 // cond(31-28) | 1110 (27-24) | 1110(23-20)| 0001 (19-16) | 2373 // cond(31-28) | 1110 (27-24) | 1110(23-20)| 0001 (19-16) |
2370 // Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0) 2374 // Rt(15-12) | 1010 (11-8) | 0(7) | 00 (6-5) | 1(4) | 0000(3-0)
2371 ASSERT(CpuFeatures::IsEnabled(VFP3)); 2375 ASSERT(CpuFeatures::IsEnabled(VFP3));
2372 emit(cond | 0xE*B24 | 0xE*B20 | B16 | 2376 emit(cond | 0xE*B24 | 0xE*B20 | B16 |
2373 dst.code()*B12 | 0xA*B8 | B4); 2377 dst.code()*B12 | 0xA*B8 | B4);
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2648 2652
2649 // Since a constant pool was just emitted, move the check offset forward by 2653 // Since a constant pool was just emitted, move the check offset forward by
2650 // the standard interval. 2654 // the standard interval.
2651 next_buffer_check_ = pc_offset() + kCheckConstInterval; 2655 next_buffer_check_ = pc_offset() + kCheckConstInterval;
2652 } 2656 }
2653 2657
2654 2658
2655 } } // namespace v8::internal 2659 } } // namespace v8::internal
2656 2660
2657 #endif // V8_TARGET_ARCH_ARM 2661 #endif // V8_TARGET_ARCH_ARM
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