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Issue 6113004: Version 3.0.7 (Closed) Base URL: https://v8.googlecode.com/svn/trunk
Patch Set: Created 9 years, 11 months ago
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1 // Copyright 2010 the V8 project authors. All rights reserved. 1 // Copyright 2010 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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2593 ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7)); 2593 ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7));
2594 ASSERT(((instr->Opc2Field() == 0x4) || (instr->Opc2Field() == 0x5)) && 2594 ASSERT(((instr->Opc2Field() == 0x4) || (instr->Opc2Field() == 0x5)) &&
2595 (instr->Opc3Field() & 0x1)); 2595 (instr->Opc3Field() & 0x1));
2596 // Comparison. 2596 // Comparison.
2597 2597
2598 VFPRegPrecision precision = kSinglePrecision; 2598 VFPRegPrecision precision = kSinglePrecision;
2599 if (instr->SzField() == 1) { 2599 if (instr->SzField() == 1) {
2600 precision = kDoublePrecision; 2600 precision = kDoublePrecision;
2601 } 2601 }
2602 2602
2603 if (instr->Bit(7) != 0) {
2604 // Raising exceptions for quiet NaNs are not supported.
2605 UNIMPLEMENTED(); // Not used by V8.
2606 }
2607
2608 int d = instr->VFPDRegCode(precision); 2603 int d = instr->VFPDRegCode(precision);
2609 int m = 0; 2604 int m = 0;
2610 if (instr->Opc2Field() == 0x4) { 2605 if (instr->Opc2Field() == 0x4) {
2611 m = instr->VFPMRegCode(precision); 2606 m = instr->VFPMRegCode(precision);
2612 } 2607 }
2613 2608
2614 if (precision == kDoublePrecision) { 2609 if (precision == kDoublePrecision) {
2615 double dd_value = get_double_from_d_register(d); 2610 double dd_value = get_double_from_d_register(d);
2616 double dm_value = 0.0; 2611 double dm_value = 0.0;
2617 if (instr->Opc2Field() == 0x4) { 2612 if (instr->Opc2Field() == 0x4) {
2618 dm_value = get_double_from_d_register(m); 2613 dm_value = get_double_from_d_register(m);
2619 } 2614 }
2620 2615
2616 // Raise exceptions for quiet NaNs if necessary.
2617 if (instr->Bit(7) == 1) {
2618 if (isnan(dd_value)) {
2619 inv_op_vfp_flag_ = true;
2620 }
2621 }
2622
2621 Compute_FPSCR_Flags(dd_value, dm_value); 2623 Compute_FPSCR_Flags(dd_value, dm_value);
2622 } else { 2624 } else {
2623 UNIMPLEMENTED(); // Not used by V8. 2625 UNIMPLEMENTED(); // Not used by V8.
2624 } 2626 }
2625 } 2627 }
2626 2628
2627 2629
2628 void Simulator::DecodeVCVTBetweenDoubleAndSingle(Instr* instr) { 2630 void Simulator::DecodeVCVTBetweenDoubleAndSingle(Instr* instr) {
2629 ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7)); 2631 ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7));
2630 ASSERT((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3)); 2632 ASSERT((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3));
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3044 uintptr_t address = *stack_slot; 3046 uintptr_t address = *stack_slot;
3045 set_register(sp, current_sp + sizeof(uintptr_t)); 3047 set_register(sp, current_sp + sizeof(uintptr_t));
3046 return address; 3048 return address;
3047 } 3049 }
3048 3050
3049 } } // namespace assembler::arm 3051 } } // namespace assembler::arm
3050 3052
3051 #endif // USE_SIMULATOR 3053 #endif // USE_SIMULATOR
3052 3054
3053 #endif // V8_TARGET_ARCH_ARM 3055 #endif // V8_TARGET_ARCH_ARM
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