Forking disassembler and simulator for Thumb2 support;...

src/arm/assembler-thumb2-inl.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 95 matching lines @@
 Address* RelocInfo::target_reference_address() {
   ASSERT(rmode_ == EXTERNAL_REFERENCE);
   return reinterpret_cast<Address*>(Assembler::target_address_address_at(pc_));
 }
 
 
 Address RelocInfo::call_address() {
   ASSERT(IsPatchedReturnSequence());
   // The 2 instructions offset assumes patched return sequence.
   ASSERT(IsJSReturn(rmode()));
-  return Memory::Address_at(pc_ + 2 * Assembler::kInstrSize);
+  return Memory::Address_at(pc_ + 2 * Assembler::kInstrArmSize);
 }
 
 
 void RelocInfo::set_call_address(Address target) {
   ASSERT(IsPatchedReturnSequence());
   // The 2 instructions offset assumes patched return sequence.
   ASSERT(IsJSReturn(rmode()));
-  Memory::Address_at(pc_ + 2 * Assembler::kInstrSize) = target;
+  Memory::Address_at(pc_ + 2 * Assembler::kInstrArmSize) = target;
 }
 
 
 Object* RelocInfo::call_object() {
   return *call_object_address();
 }
 
 
 Object** RelocInfo::call_object_address() {
   ASSERT(IsPatchedReturnSequence());
   // The 2 instructions offset assumes patched return sequence.
   ASSERT(IsJSReturn(rmode()));
-  return reinterpret_cast<Object**>(pc_ + 2 * Assembler::kInstrSize);
+  return reinterpret_cast<Object**>(pc_ + 2 * Assembler::kInstrArmSize);
 }
 
 
 void RelocInfo::set_call_object(Object* target) {
   *call_object_address() = target;
 }
 
 
 bool RelocInfo::IsPatchedReturnSequence() {
   // On ARM a "call instruction" is actually two instructions.
   //   mov lr, pc
   //   ldr pc, [pc, #XXX]
-  return (Assembler::instr_at(pc_) == kMovLrPc)
-          && ((Assembler::instr_at(pc_ + Assembler::kInstrSize) & kLdrPCPattern)
-              == kLdrPCPattern);
+  return (Assembler::instr_arm_at(pc_) == kMovLrPc) &&
+      ((Assembler::instr_arm_at(pc_ + Assembler::kInstrArmSize) &
+          kLdrPCPattern) == kLdrPCPattern);
 }
 
 
 Operand::Operand(int32_t immediate, RelocInfo::Mode rmode)  {
   rm_ = no_reg;
   imm32_ = immediate;
   rmode_ = rmode;
 }
 
 
@@ skipping 50 matching lines @@
 
 void Assembler::CheckBuffer() {
   if (buffer_space() <= kGap) {
     GrowBuffer();
   }
   if (pc_offset() >= next_buffer_check_) {
     CheckConstPool(false, true);
   }
 }
 
+void Assembler::EnsureArmMode() {
+  if (thumb_mode_) {
+    ASSERT((pc_offset() & 1) == 0);
+    if (pc_offset() & 2 != 0) {
+      DataProcessingImm(ADD, LeaveCC, pc, pc, 1);
+      // Pad with a T1 NOP
+      emit_thumb((int16_t) (b1011 * B12 | b1111 * B8));
+    } else {
+      DataProcessingImm(SUB, LeaveCC, pc, pc, 1);
+    }
+    ASSERT((pc_offset() & 3) == 0);
+    thumb_mode_ = false;
+  }
+  CheckBuffer();
+}
 
-void Assembler::emit(Instr x) {
+void Assembler::EnsureThumbMode() {
+  if (!thumb_mode_) {
+    ASSERT((pc_offset() & 1) == 0);
+    emit_arm(al | B25 | B22 | pc.code() * B16 | pc.code() * B12 | 3);
+    thumb_mode_ = true;
+    ASSERT((pc_offset() & 1) == 0);
+  }
   CheckBuffer();
-  *reinterpret_cast<Instr*>(pc_) = x;
-  pc_ += kInstrSize;
+}
+
+void Assembler::emit_arm(InstrArm x) {
+  EnsureArmMode();
+  *reinterpret_cast<InstrArm*>(pc_) = x;
+  pc_ += kInstrArmSize;
+}
+
+void Assembler::emit_int32(int32_t x) {
+  CheckBuffer();
+  *reinterpret_cast<int32_t*>(pc_) = x;
+  pc_ += sizeof(int32_t);
 }
 
 
+void Assembler::emit_thumb(InstrThumb x) {
+  EnsureThumbMode();
+  *reinterpret_cast<InstrThumb*>(pc_) = x;
+  pc_ += kInstrThumbSize;
+}
+
 Address Assembler::target_address_address_at(Address pc) {
-  Instr instr = Memory::int32_at(pc);
-  // Verify that the instruction at pc is a ldr<cond> <Rd>, [pc +/- offset_12].
+  Address target_pc = pc;
+  InstrArm instr = Memory::int32_at(target_pc);
+  // If we have a bx instruction, the instruction before the bx is
+  // what we need to patch.
+  static const int32_t kBxInstMask = 0x0ffffff0;
+  static const int32_t kBxInstPattern = 0x012fff10;
+  if ((instr & kBxInstMask) == kBxInstPattern) {
+    target_pc -= kInstrArmSize;
+    instr = Memory::int32_at(target_pc);
+  }
+  // Verify that the instruction to patch is a
+  // ldr<cond> <Rd>, [pc +/- offset_12].
   ASSERT((instr & 0x0f7f0000) == 0x051f0000);
   int offset = instr & 0xfff;  // offset_12 is unsigned
   if ((instr & (1 << 23)) == 0) offset = -offset;  // U bit defines offset sign
   // Verify that the constant pool comes after the instruction referencing it.
   ASSERT(offset >= -4);
-  return pc + offset + 8;
+  return target_pc + offset + 8;
 }
 
 
 Address Assembler::target_address_at(Address pc) {
   return Memory::Address_at(target_address_address_at(pc));
 }
 
 
 void Assembler::set_target_at(Address constant_pool_entry,
                               Address target) {
   Memory::Address_at(constant_pool_entry) = target;
 }
 
 
 void Assembler::set_target_address_at(Address pc, Address target) {
   Memory::Address_at(target_address_address_at(pc)) = target;
   // Intuitively, we would think it is necessary to flush the instruction cache
   // after patching a target address in the code as follows:
   //   CPU::FlushICache(pc, sizeof(target));
   // However, on ARM, no instruction was actually patched by the assignment
   // above; the target address is not part of an instruction, it is patched in
   // the constant pool and is read via a data access; the instruction accessing
   // this address in the constant pool remains unchanged.
 }
 
 } }  // namespace v8::internal
 
 #endif  // V8_ARM_ASSEMBLER_THUMB2_INL_H_