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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE | 23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, | 24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | 25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | 26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | 27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | 28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | 29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED | 30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED |
31 // OF THE POSSIBILITY OF SUCH DAMAGE. | 31 // OF THE POSSIBILITY OF SUCH DAMAGE. |
32 | 32 |
33 // The original source code covered by the above license above has been modified | 33 // The original source code covered by the above license above has been |
34 // significantly by Google Inc. | 34 // modified significantly by Google Inc. |
35 // Copyright 2006-2008 the V8 project authors. All rights reserved. | 35 // Copyright 2010 the V8 project authors. All rights reserved. |
36 | 36 |
37 // A light-weight ARM Assembler | 37 // A light-weight ARM Assembler |
38 // Generates user mode instructions for the ARM architecture up to version 5 | 38 // Generates user mode instructions for the ARM architecture up to version 5 |
39 | 39 |
40 #ifndef V8_ARM_ASSEMBLER_THUMB2_H_ | 40 #ifndef V8_ARM_ASSEMBLER_THUMB2_H_ |
41 #define V8_ARM_ASSEMBLER_THUMB2_H_ | 41 #define V8_ARM_ASSEMBLER_THUMB2_H_ |
42 #include <stdio.h> | 42 #include <stdio.h> |
43 #include "assembler.h" | 43 #include "assembler.h" |
44 #include "serialize.h" | 44 #include "serialize.h" |
45 | 45 |
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243 p9 = 9, | 243 p9 = 9, |
244 p10 = 10, | 244 p10 = 10, |
245 p11 = 11, | 245 p11 = 11, |
246 p12 = 12, | 246 p12 = 12, |
247 p13 = 13, | 247 p13 = 13, |
248 p14 = 14, | 248 p14 = 14, |
249 p15 = 15 | 249 p15 = 15 |
250 }; | 250 }; |
251 | 251 |
252 | 252 |
253 // Condition field in instructions | 253 // Condition field in instructions. |
254 enum Condition { | 254 enum Condition { |
255 eq = 0 << 28, // Z set equal. | 255 eq = 0 << 28, // Z set equal. |
256 ne = 1 << 28, // Z clear not equal. | 256 ne = 1 << 28, // Z clear not equal. |
257 nz = 1 << 28, // Z clear not zero. | 257 nz = 1 << 28, // Z clear not zero. |
258 cs = 2 << 28, // C set carry set. | 258 cs = 2 << 28, // C set carry set. |
259 hs = 2 << 28, // C set unsigned higher or same. | 259 hs = 2 << 28, // C set unsigned higher or same. |
260 cc = 3 << 28, // C clear carry clear. | 260 cc = 3 << 28, // C clear carry clear. |
261 lo = 3 << 28, // C clear unsigned lower. | 261 lo = 3 << 28, // C clear unsigned lower. |
262 mi = 4 << 28, // N set negative. | 262 mi = 4 << 28, // N set negative. |
263 pl = 5 << 28, // N clear positive or zero. | 263 pl = 5 << 28, // N clear positive or zero. |
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391 // Machine instruction Operands | 391 // Machine instruction Operands |
392 | 392 |
393 // Class Operand represents a shifter operand in data processing instructions | 393 // Class Operand represents a shifter operand in data processing instructions |
394 class Operand BASE_EMBEDDED { | 394 class Operand BASE_EMBEDDED { |
395 public: | 395 public: |
396 // immediate | 396 // immediate |
397 INLINE(explicit Operand(int32_t immediate, | 397 INLINE(explicit Operand(int32_t immediate, |
398 RelocInfo::Mode rmode = RelocInfo::NONE)); | 398 RelocInfo::Mode rmode = RelocInfo::NONE)); |
399 INLINE(explicit Operand(const ExternalReference& f)); | 399 INLINE(explicit Operand(const ExternalReference& f)); |
400 INLINE(explicit Operand(const char* s)); | 400 INLINE(explicit Operand(const char* s)); |
401 INLINE(explicit Operand(Object** opp)); | |
402 INLINE(explicit Operand(Context** cpp)); | |
403 explicit Operand(Handle<Object> handle); | 401 explicit Operand(Handle<Object> handle); |
404 INLINE(explicit Operand(Smi* value)); | 402 INLINE(explicit Operand(Smi* value)); |
405 | 403 |
406 // rm | 404 // rm |
407 INLINE(explicit Operand(Register rm)); | 405 INLINE(explicit Operand(Register rm)); |
408 | 406 |
409 // rm <shift_op> shift_imm | 407 // rm <shift_op> shift_imm |
410 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm); | 408 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm); |
411 | 409 |
412 // rm <shift_op> rs | 410 // rm <shift_op> rs |
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623 // Convenience branch instructions using labels | 621 // Convenience branch instructions using labels |
624 void b(Label* L, Condition cond = al) { | 622 void b(Label* L, Condition cond = al) { |
625 b(branch_offset(L, cond == al), cond); | 623 b(branch_offset(L, cond == al), cond); |
626 } | 624 } |
627 void b(Condition cond, Label* L) { b(branch_offset(L, cond == al), cond); } | 625 void b(Condition cond, Label* L) { b(branch_offset(L, cond == al), cond); } |
628 void bl(Label* L, Condition cond = al) { bl(branch_offset(L, false), cond); } | 626 void bl(Label* L, Condition cond = al) { bl(branch_offset(L, false), cond); } |
629 void bl(Condition cond, Label* L) { bl(branch_offset(L, false), cond); } | 627 void bl(Condition cond, Label* L) { bl(branch_offset(L, false), cond); } |
630 void blx(Label* L) { blx(branch_offset(L, false)); } // v5 and above | 628 void blx(Label* L) { blx(branch_offset(L, false)); } // v5 and above |
631 | 629 |
632 // Data-processing instructions | 630 // Data-processing instructions |
| 631 void ubfx(Register dst, Register src1, const Operand& src2, |
| 632 const Operand& src3, Condition cond = al); |
| 633 |
633 void and_(Register dst, Register src1, const Operand& src2, | 634 void and_(Register dst, Register src1, const Operand& src2, |
634 SBit s = LeaveCC, Condition cond = al); | 635 SBit s = LeaveCC, Condition cond = al); |
635 | 636 |
636 void eor(Register dst, Register src1, const Operand& src2, | 637 void eor(Register dst, Register src1, const Operand& src2, |
637 SBit s = LeaveCC, Condition cond = al); | 638 SBit s = LeaveCC, Condition cond = al); |
638 | 639 |
639 void sub(Register dst, Register src1, const Operand& src2, | 640 void sub(Register dst, Register src1, const Operand& src2, |
640 SBit s = LeaveCC, Condition cond = al); | 641 SBit s = LeaveCC, Condition cond = al); |
641 void sub(Register dst, Register src1, Register src2, | 642 void sub(Register dst, Register src1, Register src2, |
642 SBit s = LeaveCC, Condition cond = al) { | 643 SBit s = LeaveCC, Condition cond = al) { |
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789 LFlag l = Short); // v5 and above | 790 LFlag l = Short); // v5 and above |
790 void stc2(Coprocessor coproc, CRegister crd, Register base, int option, | 791 void stc2(Coprocessor coproc, CRegister crd, Register base, int option, |
791 LFlag l = Short); // v5 and above | 792 LFlag l = Short); // v5 and above |
792 | 793 |
793 // Support for VFP. | 794 // Support for VFP. |
794 // All these APIs support S0 to S31 and D0 to D15. | 795 // All these APIs support S0 to S31 and D0 to D15. |
795 // Currently these APIs do not support extended D registers, i.e, D16 to D31. | 796 // Currently these APIs do not support extended D registers, i.e, D16 to D31. |
796 // However, some simple modifications can allow | 797 // However, some simple modifications can allow |
797 // these APIs to support D16 to D31. | 798 // these APIs to support D16 to D31. |
798 | 799 |
| 800 void vldr(const DwVfpRegister dst, |
| 801 const Register base, |
| 802 int offset, // Offset must be a multiple of 4. |
| 803 const Condition cond = al); |
| 804 void vstr(const DwVfpRegister src, |
| 805 const Register base, |
| 806 int offset, // Offset must be a multiple of 4. |
| 807 const Condition cond = al); |
799 void vmov(const DwVfpRegister dst, | 808 void vmov(const DwVfpRegister dst, |
800 const Register src1, | 809 const Register src1, |
801 const Register src2, | 810 const Register src2, |
802 const Condition cond = al); | 811 const Condition cond = al); |
803 void vmov(const Register dst1, | 812 void vmov(const Register dst1, |
804 const Register dst2, | 813 const Register dst2, |
805 const DwVfpRegister src, | 814 const DwVfpRegister src, |
806 const Condition cond = al); | 815 const Condition cond = al); |
807 void vmov(const SwVfpRegister dst, | 816 void vmov(const SwVfpRegister dst, |
808 const Register src, | 817 const Register src, |
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1018 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); | 1027 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); |
1019 | 1028 |
1020 friend class RegExpMacroAssemblerARM; | 1029 friend class RegExpMacroAssemblerARM; |
1021 friend class RelocInfo; | 1030 friend class RelocInfo; |
1022 friend class CodePatcher; | 1031 friend class CodePatcher; |
1023 }; | 1032 }; |
1024 | 1033 |
1025 } } // namespace v8::internal | 1034 } } // namespace v8::internal |
1026 | 1035 |
1027 #endif // V8_ARM_ASSEMBLER_THUMB2_H_ | 1036 #endif // V8_ARM_ASSEMBLER_THUMB2_H_ |
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