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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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167 } | 167 } |
168 | 168 |
169 | 169 |
170 Operand::Operand(const ExternalReference& f) { | 170 Operand::Operand(const ExternalReference& f) { |
171 rm_ = no_reg; | 171 rm_ = no_reg; |
172 imm32_ = reinterpret_cast<int32_t>(f.address()); | 172 imm32_ = reinterpret_cast<int32_t>(f.address()); |
173 rmode_ = RelocInfo::EXTERNAL_REFERENCE; | 173 rmode_ = RelocInfo::EXTERNAL_REFERENCE; |
174 } | 174 } |
175 | 175 |
176 | 176 |
177 Operand::Operand(Object** opp) { | |
178 rm_ = no_reg; | |
179 imm32_ = reinterpret_cast<int32_t>(opp); | |
180 rmode_ = RelocInfo::NONE; | |
181 } | |
182 | |
183 | |
184 Operand::Operand(Context** cpp) { | |
185 rm_ = no_reg; | |
186 imm32_ = reinterpret_cast<int32_t>(cpp); | |
187 rmode_ = RelocInfo::NONE; | |
188 } | |
189 | |
190 | |
191 Operand::Operand(Smi* value) { | 177 Operand::Operand(Smi* value) { |
192 rm_ = no_reg; | 178 rm_ = no_reg; |
193 imm32_ = reinterpret_cast<intptr_t>(value); | 179 imm32_ = reinterpret_cast<intptr_t>(value); |
194 rmode_ = RelocInfo::NONE; | 180 rmode_ = RelocInfo::NONE; |
195 } | 181 } |
196 | 182 |
197 | 183 |
198 Operand::Operand(Register rm) { | 184 Operand::Operand(Register rm) { |
199 rm_ = rm; | 185 rm_ = rm; |
200 rs_ = no_reg; | 186 rs_ = no_reg; |
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222 | 208 |
223 | 209 |
224 void Assembler::emit(Instr x) { | 210 void Assembler::emit(Instr x) { |
225 CheckBuffer(); | 211 CheckBuffer(); |
226 *reinterpret_cast<Instr*>(pc_) = x; | 212 *reinterpret_cast<Instr*>(pc_) = x; |
227 pc_ += kInstrSize; | 213 pc_ += kInstrSize; |
228 } | 214 } |
229 | 215 |
230 | 216 |
231 Address Assembler::target_address_address_at(Address pc) { | 217 Address Assembler::target_address_address_at(Address pc) { |
232 Instr instr = Memory::int32_at(pc); | 218 Address target_pc = pc; |
233 // Verify that the instruction at pc is a ldr<cond> <Rd>, [pc +/- offset_12]. | 219 Instr instr = Memory::int32_at(target_pc); |
| 220 // If we have a bx instruction, the instruction before the bx is |
| 221 // what we need to patch. |
| 222 static const int32_t kBxInstMask = 0x0ffffff0; |
| 223 static const int32_t kBxInstPattern = 0x012fff10; |
| 224 if ((instr & kBxInstMask) == kBxInstPattern) { |
| 225 target_pc -= kInstrSize; |
| 226 instr = Memory::int32_at(target_pc); |
| 227 } |
| 228 // Verify that the instruction to patch is a |
| 229 // ldr<cond> <Rd>, [pc +/- offset_12]. |
234 ASSERT((instr & 0x0f7f0000) == 0x051f0000); | 230 ASSERT((instr & 0x0f7f0000) == 0x051f0000); |
235 int offset = instr & 0xfff; // offset_12 is unsigned | 231 int offset = instr & 0xfff; // offset_12 is unsigned |
236 if ((instr & (1 << 23)) == 0) offset = -offset; // U bit defines offset sign | 232 if ((instr & (1 << 23)) == 0) offset = -offset; // U bit defines offset sign |
237 // Verify that the constant pool comes after the instruction referencing it. | 233 // Verify that the constant pool comes after the instruction referencing it. |
238 ASSERT(offset >= -4); | 234 ASSERT(offset >= -4); |
239 return pc + offset + 8; | 235 return target_pc + offset + 8; |
240 } | 236 } |
241 | 237 |
242 | 238 |
243 Address Assembler::target_address_at(Address pc) { | 239 Address Assembler::target_address_at(Address pc) { |
244 return Memory::Address_at(target_address_address_at(pc)); | 240 return Memory::Address_at(target_address_address_at(pc)); |
245 } | 241 } |
246 | 242 |
247 | 243 |
248 void Assembler::set_target_at(Address constant_pool_entry, | 244 void Assembler::set_target_at(Address constant_pool_entry, |
249 Address target) { | 245 Address target) { |
250 Memory::Address_at(constant_pool_entry) = target; | 246 Memory::Address_at(constant_pool_entry) = target; |
251 } | 247 } |
252 | 248 |
253 | 249 |
254 void Assembler::set_target_address_at(Address pc, Address target) { | 250 void Assembler::set_target_address_at(Address pc, Address target) { |
255 Memory::Address_at(target_address_address_at(pc)) = target; | 251 Memory::Address_at(target_address_address_at(pc)) = target; |
256 // Intuitively, we would think it is necessary to flush the instruction cache | 252 // Intuitively, we would think it is necessary to flush the instruction cache |
257 // after patching a target address in the code as follows: | 253 // after patching a target address in the code as follows: |
258 // CPU::FlushICache(pc, sizeof(target)); | 254 // CPU::FlushICache(pc, sizeof(target)); |
259 // However, on ARM, no instruction was actually patched by the assignment | 255 // However, on ARM, no instruction was actually patched by the assignment |
260 // above; the target address is not part of an instruction, it is patched in | 256 // above; the target address is not part of an instruction, it is patched in |
261 // the constant pool and is read via a data access; the instruction accessing | 257 // the constant pool and is read via a data access; the instruction accessing |
262 // this address in the constant pool remains unchanged. | 258 // this address in the constant pool remains unchanged. |
263 } | 259 } |
264 | 260 |
265 } } // namespace v8::internal | 261 } } // namespace v8::internal |
266 | 262 |
267 #endif // V8_ARM_ASSEMBLER_THUMB2_INL_H_ | 263 #endif // V8_ARM_ASSEMBLER_THUMB2_INL_H_ |
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