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1 // Copyright 2010 the V8 project authors. All rights reserved. | 1 // Copyright 2010 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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1053 if (FLAG_debug_code) { | 1053 if (FLAG_debug_code) { |
1054 // Trash the registers to simulate an allocation failure. | 1054 // Trash the registers to simulate an allocation failure. |
1055 mov(result, Operand(0x7091)); | 1055 mov(result, Operand(0x7091)); |
1056 mov(scratch1, Operand(0x7191)); | 1056 mov(scratch1, Operand(0x7191)); |
1057 mov(scratch2, Operand(0x7291)); | 1057 mov(scratch2, Operand(0x7291)); |
1058 } | 1058 } |
1059 jmp(gc_required); | 1059 jmp(gc_required); |
1060 return; | 1060 return; |
1061 } | 1061 } |
1062 | 1062 |
1063 // Assert that the register arguments are different and that none of | |
1064 // them are ip. ip is used explicitly in the code generated below. | |
1065 ASSERT(!result.is(scratch1)); | 1063 ASSERT(!result.is(scratch1)); |
1066 ASSERT(!result.is(scratch2)); | 1064 ASSERT(!result.is(scratch2)); |
1067 ASSERT(!scratch1.is(scratch2)); | 1065 ASSERT(!scratch1.is(scratch2)); |
1068 ASSERT(!result.is(ip)); | |
1069 ASSERT(!scratch1.is(ip)); | |
1070 ASSERT(!scratch2.is(ip)); | |
1071 | 1066 |
1072 // Check relative positions of allocation top and limit addresses. | 1067 // Check relative positions of allocation top and limit addresses. |
1073 // The values must be adjacent in memory to allow the use of LDM. | 1068 // The values must be adjacent in memory to allow the use of LDM. |
1074 // Also, assert that the registers are numbered such that the values | 1069 // Also, assert that the registers are numbered such that the values |
1075 // are loaded in the correct order. | 1070 // are loaded in the correct order. |
1076 ExternalReference new_space_allocation_top = | 1071 ExternalReference new_space_allocation_top = |
1077 ExternalReference::new_space_allocation_top_address(); | 1072 ExternalReference::new_space_allocation_top_address(); |
1078 ExternalReference new_space_allocation_limit = | 1073 ExternalReference new_space_allocation_limit = |
1079 ExternalReference::new_space_allocation_limit_address(); | 1074 ExternalReference::new_space_allocation_limit_address(); |
1080 intptr_t top = | 1075 intptr_t top = |
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2107 | 2102 |
2108 void CodePatcher::Emit(Address addr) { | 2103 void CodePatcher::Emit(Address addr) { |
2109 masm()->emit(reinterpret_cast<Instr>(addr)); | 2104 masm()->emit(reinterpret_cast<Instr>(addr)); |
2110 } | 2105 } |
2111 #endif // ENABLE_DEBUGGER_SUPPORT | 2106 #endif // ENABLE_DEBUGGER_SUPPORT |
2112 | 2107 |
2113 | 2108 |
2114 } } // namespace v8::internal | 2109 } } // namespace v8::internal |
2115 | 2110 |
2116 #endif // V8_TARGET_ARCH_ARM | 2111 #endif // V8_TARGET_ARCH_ARM |
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