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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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2402 void Assembler::movsd(XMMRegister dst, const Operand& src) { | 2402 void Assembler::movsd(XMMRegister dst, const Operand& src) { |
2403 ASSERT(CpuFeatures::IsEnabled(SSE2)); | 2403 ASSERT(CpuFeatures::IsEnabled(SSE2)); |
2404 EnsureSpace ensure_space(this); | 2404 EnsureSpace ensure_space(this); |
2405 last_pc_ = pc_; | 2405 last_pc_ = pc_; |
2406 EMIT(0xF2); // double | 2406 EMIT(0xF2); // double |
2407 EMIT(0x0F); | 2407 EMIT(0x0F); |
2408 EMIT(0x10); // load | 2408 EMIT(0x10); // load |
2409 emit_sse_operand(dst, src); | 2409 emit_sse_operand(dst, src); |
2410 } | 2410 } |
2411 | 2411 |
2412 | |
2413 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | 2412 void Assembler::movsd(XMMRegister dst, XMMRegister src) { |
2414 ASSERT(CpuFeatures::IsEnabled(SSE2)); | 2413 ASSERT(CpuFeatures::IsEnabled(SSE2)); |
2415 EnsureSpace ensure_space(this); | 2414 EnsureSpace ensure_space(this); |
2416 last_pc_ = pc_; | 2415 last_pc_ = pc_; |
2417 EMIT(0xF2); | 2416 EMIT(0xF2); |
2418 EMIT(0x0F); | 2417 EMIT(0x0F); |
2419 EMIT(0x10); | 2418 EMIT(0x10); |
2420 emit_sse_operand(dst, src); | 2419 emit_sse_operand(dst, src); |
2421 } | 2420 } |
2422 | 2421 |
2423 | 2422 |
2424 void Assembler::movd(XMMRegister dst, const Operand& src) { | 2423 void Assembler::movd(XMMRegister dst, const Operand& src) { |
2425 ASSERT(CpuFeatures::IsEnabled(SSE2)); | 2424 ASSERT(CpuFeatures::IsEnabled(SSE2)); |
2426 EnsureSpace ensure_space(this); | 2425 EnsureSpace ensure_space(this); |
2427 last_pc_ = pc_; | 2426 last_pc_ = pc_; |
2428 EMIT(0x66); | 2427 EMIT(0x66); |
2429 EMIT(0x0F); | 2428 EMIT(0x0F); |
2430 EMIT(0x6E); | 2429 EMIT(0x6E); |
2431 emit_sse_operand(dst, src); | 2430 emit_sse_operand(dst, src); |
2432 } | 2431 } |
2433 | 2432 |
2434 | 2433 |
2435 void Assembler::movd(const Operand& dst, XMMRegister src) { | |
2436 ASSERT(CpuFeatures::IsEnabled(SSE2)); | |
2437 EnsureSpace ensure_space(this); | |
2438 last_pc_ = pc_; | |
2439 EMIT(0x66); | |
2440 EMIT(0x0F); | |
2441 EMIT(0x7E); | |
2442 emit_sse_operand(src, dst); | |
2443 } | |
2444 | |
2445 | |
2446 void Assembler::pand(XMMRegister dst, XMMRegister src) { | 2434 void Assembler::pand(XMMRegister dst, XMMRegister src) { |
2447 ASSERT(CpuFeatures::IsEnabled(SSE2)); | 2435 ASSERT(CpuFeatures::IsEnabled(SSE2)); |
2448 EnsureSpace ensure_space(this); | 2436 EnsureSpace ensure_space(this); |
2449 last_pc_ = pc_; | 2437 last_pc_ = pc_; |
2450 EMIT(0x66); | 2438 EMIT(0x66); |
2451 EMIT(0x0F); | 2439 EMIT(0x0F); |
2452 EMIT(0xDB); | 2440 EMIT(0xDB); |
2453 emit_sse_operand(dst, src); | 2441 emit_sse_operand(dst, src); |
2454 } | 2442 } |
2455 | 2443 |
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2470 EnsureSpace ensure_space(this); | 2458 EnsureSpace ensure_space(this); |
2471 last_pc_ = pc_; | 2459 last_pc_ = pc_; |
2472 EMIT(0x66); | 2460 EMIT(0x66); |
2473 EMIT(0x0F); | 2461 EMIT(0x0F); |
2474 EMIT(0x38); | 2462 EMIT(0x38); |
2475 EMIT(0x17); | 2463 EMIT(0x17); |
2476 emit_sse_operand(dst, src); | 2464 emit_sse_operand(dst, src); |
2477 } | 2465 } |
2478 | 2466 |
2479 | 2467 |
2480 void Assembler::psllq(XMMRegister reg, int8_t shift) { | 2468 void Assembler::psllq(XMMRegister reg, int8_t imm8) { |
2481 ASSERT(CpuFeatures::IsEnabled(SSE2)); | 2469 ASSERT(CpuFeatures::IsEnabled(SSE2)); |
2482 EnsureSpace ensure_space(this); | 2470 EnsureSpace ensure_space(this); |
2483 last_pc_ = pc_; | 2471 last_pc_ = pc_; |
2484 EMIT(0x66); | 2472 EMIT(0x66); |
2485 EMIT(0x0F); | 2473 EMIT(0x0F); |
2486 EMIT(0x73); | 2474 EMIT(0x73); |
2487 emit_sse_operand(esi, reg); // esi == 6 | 2475 emit_sse_operand(esi, reg); // esi == 6 |
2488 EMIT(shift); | 2476 EMIT(imm8); |
2489 } | |
2490 | |
2491 | |
2492 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int8_t shuffle) { | |
2493 ASSERT(CpuFeatures::IsEnabled(SSE2)); | |
2494 EnsureSpace ensure_space(this); | |
2495 last_pc_ = pc_; | |
2496 EMIT(0x66); | |
2497 EMIT(0x0F); | |
2498 EMIT(0x70); | |
2499 emit_sse_operand(dst, src); | |
2500 EMIT(shuffle); | |
2501 } | |
2502 | |
2503 | |
2504 void Assembler::pextrd(const Operand& dst, XMMRegister src, int8_t offset) { | |
2505 ASSERT(CpuFeatures::IsEnabled(SSE2)); | |
2506 EnsureSpace ensure_space(this); | |
2507 last_pc_ = pc_; | |
2508 EMIT(0x66); | |
2509 EMIT(0x0F); | |
2510 EMIT(0x3A); | |
2511 EMIT(0x16); | |
2512 emit_sse_operand(src, dst); | |
2513 EMIT(offset); | |
2514 } | 2477 } |
2515 | 2478 |
2516 | 2479 |
2517 void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) { | 2480 void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) { |
2518 Register ireg = { reg.code() }; | 2481 Register ireg = { reg.code() }; |
2519 emit_operand(ireg, adr); | 2482 emit_operand(ireg, adr); |
2520 } | 2483 } |
2521 | 2484 |
2522 | 2485 |
2523 void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) { | 2486 void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) { |
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2733 fprintf(coverage_log, "%s\n", file_line); | 2696 fprintf(coverage_log, "%s\n", file_line); |
2734 fflush(coverage_log); | 2697 fflush(coverage_log); |
2735 } | 2698 } |
2736 } | 2699 } |
2737 | 2700 |
2738 #endif | 2701 #endif |
2739 | 2702 |
2740 } } // namespace v8::internal | 2703 } } // namespace v8::internal |
2741 | 2704 |
2742 #endif // V8_TARGET_ARCH_IA32 | 2705 #endif // V8_TARGET_ARCH_IA32 |
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