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Side by Side Diff: src/arm/simulator-arm.cc

Issue 573027: ARMv7 ubfx support... (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: Created 10 years, 10 months ago
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1 // Copyright 2010 the V8 project authors. All rights reserved. 1 // Copyright 2010 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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1734 if (instr->HasL()) { 1734 if (instr->HasL()) {
1735 set_register(rd, ReadW(addr, instr)); 1735 set_register(rd, ReadW(addr, instr));
1736 } else { 1736 } else {
1737 WriteW(addr, get_register(rd), instr); 1737 WriteW(addr, get_register(rd), instr);
1738 } 1738 }
1739 } 1739 }
1740 } 1740 }
1741 1741
1742 1742
1743 void Simulator::DecodeType3(Instr* instr) { 1743 void Simulator::DecodeType3(Instr* instr) {
1744 ASSERT(instr->Bit(4) == 0); 1744 ASSERT(instr->Bits(6, 4) == 0x5 || instr->Bit(4) == 0);
1745 int rd = instr->RdField(); 1745 int rd = instr->RdField();
1746 int rn = instr->RnField(); 1746 int rn = instr->RnField();
1747 int32_t rn_val = get_register(rn); 1747 int32_t rn_val = get_register(rn);
1748 bool shifter_carry_out = 0; 1748 bool shifter_carry_out = 0;
1749 int32_t shifter_operand = GetShiftRm(instr, &shifter_carry_out); 1749 int32_t shifter_operand = GetShiftRm(instr, &shifter_carry_out);
1750 int32_t addr = 0; 1750 int32_t addr = 0;
1751 switch (instr->PUField()) { 1751 switch (instr->PUField()) {
1752 case 0: { 1752 case 0: {
1753 ASSERT(!instr->HasW()); 1753 ASSERT(!instr->HasW());
1754 Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm"); 1754 Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
1755 break; 1755 break;
1756 } 1756 }
1757 case 1: { 1757 case 1: {
1758 ASSERT(!instr->HasW()); 1758 ASSERT(!instr->HasW());
1759 Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm"); 1759 Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
1760 break; 1760 break;
1761 } 1761 }
1762 case 2: { 1762 case 2: {
1763 // Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w"); 1763 // Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
1764 addr = rn_val - shifter_operand; 1764 addr = rn_val - shifter_operand;
1765 if (instr->HasW()) { 1765 if (instr->HasW()) {
1766 set_register(rn, addr); 1766 set_register(rn, addr);
1767 } 1767 }
1768 break; 1768 break;
1769 } 1769 }
1770 case 3: { 1770 case 3: {
1771 // Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w"); 1771 if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) {
1772 addr = rn_val + shifter_operand; 1772 uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16));
1773 if (instr->HasW()) { 1773 uint32_t lsbit = static_cast<uint32_t>(instr->ShiftAmountField());
1774 set_register(rn, addr); 1774 uint32_t msbit = widthminus1 + lsbit;
1775 if (msbit <= 31) {
1776 uint32_t rm_val =
1777 static_cast<uint32_t>(get_register(instr->RmField()));
1778 uint32_t extr_val = rm_val << (31 - msbit);
1779 extr_val = extr_val >> (31 - widthminus1);
1780 set_register(instr->RdField(), extr_val);
1781 } else {
1782 UNREACHABLE();
1783 }
1784 return;
1785 } else {
1786 // Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
1787 addr = rn_val + shifter_operand;
1788 if (instr->HasW()) {
1789 set_register(rn, addr);
1790 }
1775 } 1791 }
1776 break; 1792 break;
1777 } 1793 }
1778 default: { 1794 default: {
1779 UNREACHABLE(); 1795 UNREACHABLE();
1780 break; 1796 break;
1781 } 1797 }
1782 } 1798 }
1783 if (instr->HasB()) { 1799 if (instr->HasB()) {
1784 if (instr->HasL()) { 1800 if (instr->HasL()) {
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2287 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp); 2303 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp);
2288 uintptr_t address = *stack_slot; 2304 uintptr_t address = *stack_slot;
2289 set_register(sp, current_sp + sizeof(uintptr_t)); 2305 set_register(sp, current_sp + sizeof(uintptr_t));
2290 return address; 2306 return address;
2291 } 2307 }
2292 2308
2293 2309
2294 } } // namespace assembler::arm 2310 } } // namespace assembler::arm
2295 2311
2296 #endif // !defined(__arm__) 2312 #endif // !defined(__arm__)
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