Add support for ldrd/strd from Kun Zhang (zhangk@codeaurora.org), Code Aurora

src/arm/assembler-arm.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 1129 matching lines @@
 void Assembler::ldrsb(Register dst, const MemOperand& src, Condition cond) {
   addrmod3(cond | L | B7 | S6 | B4, dst, src);
 }
 
 
 void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) {
   addrmod3(cond | L | B7 | S6 | H | B4, dst, src);
 }
 
 
+void Assembler::ldrd(Register dst, const MemOperand& src, Condition cond) {
+  addrmod3(cond | B7 | B6 | B4, dst, src);

[Erik Corry, 2010/05/04 07:06:13]

This instruction is not available on all CPUs.  Please generate two ldr
instructins on CPUs where it is not available.  See the macro definitions in
constants-arm.h.

[zhangk, 2010/05/07 05:32:14]

On 2010/05/04 07:06:13, Erik Corry wrote:

Done.

+}
+
+
+void Assembler::strd(Register src, const MemOperand& dst, Condition cond) {
+  addrmod3(cond | B7 | B6 | B5 | B4, src, dst);

[Erik Corry, 2010/05/04 07:06:13]

And here.

[zhangk, 2010/05/07 05:32:14]

On 2010/05/04 07:06:13, Erik Corry wrote:

Done.

+}
+
+
 // Load/Store multiple instructions
 void Assembler::ldm(BlockAddrMode am,
                     Register base,
                     RegList dst,
                     Condition cond) {
   // ABI stack constraint: ldmxx base, {..sp..}  base != sp  is not restartable
   ASSERT(base.is(sp) || (dst & sp.bit()) == 0);
 
   addrmod4(cond | B27 | am | L, base, dst);
 
@@ skipping 682 matching lines @@
     bind(&after_pool);
   }
 
   // Since a constant pool was just emitted, move the check offset forward by
   // the standard interval.
   next_buffer_check_ = pc_offset() + kCheckConstInterval;
 }
 
 
 } }  // namespace v8::internal