Fix ARM build.

src/platform-linux.cc

 // Copyright 2006-2008 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 168 matching lines @@
   return 8;
 #elif V8_TARGET_ARCH_MIPS
   return 8;
 #endif
   // With gcc 4.4 the tree vectorization optimizer can generate code
   // that requires 16 byte alignment such as movdqa on x86.
   return 16;
 }
 
 
-#ifdef V8_TARGET_ARCH_ARM
-// 0xffff0fa0 is the hard coded address of a function provided by
-// the kernel which implements a memory barrier. On older
-// ARM architecture revisions (pre-v6) this may be implemented using
-// a syscall. This address is stable, and in active use (hard coded)
-// by at least glibc-2.7 and the Android C library.
-typedef void (*LinuxKernelMemoryBarrierFunc)(void);
-LinuxKernelMemoryBarrierFunc pLinuxKernelMemoryBarrier __attribute__((weak)) =
-    (LinuxKernelMemoryBarrierFunc) 0xffff0fa0;
-#endif
-
 void OS::ReleaseStore(volatile AtomicWord* ptr, AtomicWord value) {
 #if defined(V8_TARGET_ARCH_ARM) && defined(__arm__)
   // Only use on ARM hardware.
-  pLinuxKernelMemoryBarrier();
+  MemoryBarrier();
 #else
   __asm__ __volatile__("" : : : "memory");
   // An x86 store acts as a release barrier.
 #endif
   *ptr = value;
 }
 
 
 const char* OS::LocalTimezone(double time) {
   if (isnan(time)) return "";
@@ skipping 742 matching lines @@
   }
 
   // This sampler is no longer the active sampler.
   active_sampler_ = NULL;
 }
 
 
 #endif  // ENABLE_LOGGING_AND_PROFILING
 
 } }  // namespace v8::internal