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Issue 551048: Very small optimization of ARM compare stub. (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: '' Created 10 years, 11 months ago
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1 // Copyright 2009 the V8 project authors. All rights reserved. 1 // Copyright 2009 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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883 overflow = ((left < 0 && right >= 0) || (left >= 0 && right < 0)) 883 overflow = ((left < 0 && right >= 0) || (left >= 0 && right < 0))
884 // and first operand and result have different signs 884 // and first operand and result have different signs
885 && ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0)); 885 && ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0));
886 } 886 }
887 return overflow; 887 return overflow;
888 } 888 }
889 889
890 890
891 // Support for VFP comparisons. 891 // Support for VFP comparisons.
892 void Simulator::Compute_FPSCR_Flags(double val1, double val2) { 892 void Simulator::Compute_FPSCR_Flags(double val1, double val2) {
893 if (isnan(val1) || isnan(val2)) {
894 n_flag_FPSCR_ = false;
895 z_flag_FPSCR_ = false;
896 c_flag_FPSCR_ = true;
897 v_flag_FPSCR_ = true;
893 // All non-NaN cases. 898 // All non-NaN cases.
894 if (val1 == val2) { 899 } else if (val1 == val2) {
895 n_flag_FPSCR_ = false; 900 n_flag_FPSCR_ = false;
896 z_flag_FPSCR_ = true; 901 z_flag_FPSCR_ = true;
897 c_flag_FPSCR_ = true; 902 c_flag_FPSCR_ = true;
898 v_flag_FPSCR_ = false; 903 v_flag_FPSCR_ = false;
899 } else if (val1 < val2) { 904 } else if (val1 < val2) {
900 n_flag_FPSCR_ = true; 905 n_flag_FPSCR_ = true;
901 z_flag_FPSCR_ = false; 906 z_flag_FPSCR_ = false;
902 c_flag_FPSCR_ = false; 907 c_flag_FPSCR_ = false;
903 v_flag_FPSCR_ = false; 908 v_flag_FPSCR_ = false;
904 } else { 909 } else {
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2255 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp); 2260 uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp);
2256 uintptr_t address = *stack_slot; 2261 uintptr_t address = *stack_slot;
2257 set_register(sp, current_sp + sizeof(uintptr_t)); 2262 set_register(sp, current_sp + sizeof(uintptr_t));
2258 return address; 2263 return address;
2259 } 2264 }
2260 2265
2261 2266
2262 } } // namespace assembler::arm 2267 } } // namespace assembler::arm
2263 2268
2264 #endif // !defined(__arm__) 2269 #endif // !defined(__arm__)
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