Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(190)

Side by Side Diff: src/ia32/disasm-ia32.cc

Issue 546087: Implement inline string compare on ARM. (Closed)
Patch Set: Further optimization of ARM version Created 10 years, 11 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/ia32/codegen-ia32.cc ('k') | src/ia32/macro-assembler-ia32.h » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright 2007-2008 the V8 project authors. All rights reserved. 1 // Copyright 2007-2008 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
(...skipping 35 matching lines...) Expand 10 before | Expand all | Expand 10 after
46 //------------------------------------------------------------------ 46 //------------------------------------------------------------------
47 struct ByteMnemonic { 47 struct ByteMnemonic {
48 int b; // -1 terminates, otherwise must be in range (0..255) 48 int b; // -1 terminates, otherwise must be in range (0..255)
49 const char* mnem; 49 const char* mnem;
50 OperandOrder op_order_; 50 OperandOrder op_order_;
51 }; 51 };
52 52
53 53
54 static ByteMnemonic two_operands_instr[] = { 54 static ByteMnemonic two_operands_instr[] = {
55 {0x03, "add", REG_OPER_OP_ORDER}, 55 {0x03, "add", REG_OPER_OP_ORDER},
56 {0x21, "and", OPER_REG_OP_ORDER},
57 {0x23, "and", REG_OPER_OP_ORDER},
58 {0x3B, "cmp", REG_OPER_OP_ORDER},
59 {0x8D, "lea", REG_OPER_OP_ORDER},
60 {0x09, "or", OPER_REG_OP_ORDER}, 56 {0x09, "or", OPER_REG_OP_ORDER},
61 {0x0B, "or", REG_OPER_OP_ORDER}, 57 {0x0B, "or", REG_OPER_OP_ORDER},
62 {0x1B, "sbb", REG_OPER_OP_ORDER}, 58 {0x1B, "sbb", REG_OPER_OP_ORDER},
59 {0x21, "and", OPER_REG_OP_ORDER},
60 {0x23, "and", REG_OPER_OP_ORDER},
63 {0x29, "sub", OPER_REG_OP_ORDER}, 61 {0x29, "sub", OPER_REG_OP_ORDER},
64 {0x2A, "subb", REG_OPER_OP_ORDER}, 62 {0x2A, "subb", REG_OPER_OP_ORDER},
65 {0x2B, "sub", REG_OPER_OP_ORDER}, 63 {0x2B, "sub", REG_OPER_OP_ORDER},
64 {0x31, "xor", OPER_REG_OP_ORDER},
65 {0x33, "xor", REG_OPER_OP_ORDER},
66 {0x38, "cmpb", OPER_REG_OP_ORDER},
67 {0x3A, "cmpb", REG_OPER_OP_ORDER},
68 {0x3B, "cmp", REG_OPER_OP_ORDER},
66 {0x84, "test_b", REG_OPER_OP_ORDER}, 69 {0x84, "test_b", REG_OPER_OP_ORDER},
67 {0x85, "test", REG_OPER_OP_ORDER}, 70 {0x85, "test", REG_OPER_OP_ORDER},
68 {0x31, "xor", OPER_REG_OP_ORDER},
69 {0x33, "xor", REG_OPER_OP_ORDER},
70 {0x87, "xchg", REG_OPER_OP_ORDER}, 71 {0x87, "xchg", REG_OPER_OP_ORDER},
71 {0x8A, "mov_b", REG_OPER_OP_ORDER}, 72 {0x8A, "mov_b", REG_OPER_OP_ORDER},
72 {0x8B, "mov", REG_OPER_OP_ORDER}, 73 {0x8B, "mov", REG_OPER_OP_ORDER},
74 {0x8D, "lea", REG_OPER_OP_ORDER},
73 {-1, "", UNSET_OP_ORDER} 75 {-1, "", UNSET_OP_ORDER}
74 }; 76 };
75 77
76 78
77 static ByteMnemonic zero_operands_instr[] = { 79 static ByteMnemonic zero_operands_instr[] = {
78 {0xC3, "ret", UNSET_OP_ORDER}, 80 {0xC3, "ret", UNSET_OP_ORDER},
79 {0xC9, "leave", UNSET_OP_ORDER}, 81 {0xC9, "leave", UNSET_OP_ORDER},
80 {0x90, "nop", UNSET_OP_ORDER}, 82 {0x90, "nop", UNSET_OP_ORDER},
81 {0xF4, "hlt", UNSET_OP_ORDER}, 83 {0xF4, "hlt", UNSET_OP_ORDER},
82 {0xCC, "int3", UNSET_OP_ORDER}, 84 {0xCC, "int3", UNSET_OP_ORDER},
(...skipping 1266 matching lines...) Expand 10 before | Expand all | Expand 10 after
1349 } 1351 }
1350 for (int i = 6 - (pc - prev_pc); i >= 0; i--) { 1352 for (int i = 6 - (pc - prev_pc); i >= 0; i--) {
1351 fprintf(f, " "); 1353 fprintf(f, " ");
1352 } 1354 }
1353 fprintf(f, " %s\n", buffer.start()); 1355 fprintf(f, " %s\n", buffer.start());
1354 } 1356 }
1355 } 1357 }
1356 1358
1357 1359
1358 } // namespace disasm 1360 } // namespace disasm
OLDNEW
« no previous file with comments | « src/ia32/codegen-ia32.cc ('k') | src/ia32/macro-assembler-ia32.h » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698