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Issue 545155: Add vstr and vldr floating point load and store to ARM assembler, disassemble... (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: '' Created 10 years, 11 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
31 // OF THE POSSIBILITY OF SUCH DAMAGE. 31 // OF THE POSSIBILITY OF SUCH DAMAGE.
32 32
33 // The original source code covered by the above license above has been modified 33 // The original source code covered by the above license above has been
34 // significantly by Google Inc. 34 // modified significantly by Google Inc.
35 // Copyright 2006-2008 the V8 project authors. All rights reserved. 35 // Copyright 2010 the V8 project authors. All rights reserved.
36 36
37 // A light-weight ARM Assembler 37 // A light-weight ARM Assembler
38 // Generates user mode instructions for the ARM architecture up to version 5 38 // Generates user mode instructions for the ARM architecture up to version 5
39 39
40 #ifndef V8_ARM_ASSEMBLER_ARM_H_ 40 #ifndef V8_ARM_ASSEMBLER_ARM_H_
41 #define V8_ARM_ASSEMBLER_ARM_H_ 41 #define V8_ARM_ASSEMBLER_ARM_H_
42 #include <stdio.h> 42 #include <stdio.h>
43 #include "assembler.h" 43 #include "assembler.h"
44 #include "serialize.h" 44 #include "serialize.h"
45 45
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789 LFlag l = Short); // v5 and above 789 LFlag l = Short); // v5 and above
790 void stc2(Coprocessor coproc, CRegister crd, Register base, int option, 790 void stc2(Coprocessor coproc, CRegister crd, Register base, int option,
791 LFlag l = Short); // v5 and above 791 LFlag l = Short); // v5 and above
792 792
793 // Support for VFP. 793 // Support for VFP.
794 // All these APIs support S0 to S31 and D0 to D15. 794 // All these APIs support S0 to S31 and D0 to D15.
795 // Currently these APIs do not support extended D registers, i.e, D16 to D31. 795 // Currently these APIs do not support extended D registers, i.e, D16 to D31.
796 // However, some simple modifications can allow 796 // However, some simple modifications can allow
797 // these APIs to support D16 to D31. 797 // these APIs to support D16 to D31.
798 798
799 void vldr(const DwVfpRegister dst,
800 const Register base,
801 int offset, // Offset must be a multiple of 4.
802 const Condition cond = al);
803 void vstr(const DwVfpRegister src,
804 const Register base,
805 int offset, // Offset must be a multiple of 4.
806 const Condition cond = al);
799 void vmov(const DwVfpRegister dst, 807 void vmov(const DwVfpRegister dst,
800 const Register src1, 808 const Register src1,
801 const Register src2, 809 const Register src2,
802 const Condition cond = al); 810 const Condition cond = al);
803 void vmov(const Register dst1, 811 void vmov(const Register dst1,
804 const Register dst2, 812 const Register dst2,
805 const DwVfpRegister src, 813 const DwVfpRegister src,
806 const Condition cond = al); 814 const Condition cond = al);
807 void vmov(const SwVfpRegister dst, 815 void vmov(const SwVfpRegister dst,
808 const Register src, 816 const Register src,
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1018 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); 1026 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1019 1027
1020 friend class RegExpMacroAssemblerARM; 1028 friend class RegExpMacroAssemblerARM;
1021 friend class RelocInfo; 1029 friend class RelocInfo;
1022 friend class CodePatcher; 1030 friend class CodePatcher;
1023 }; 1031 };
1024 1032
1025 } } // namespace v8::internal 1033 } } // namespace v8::internal
1026 1034
1027 #endif // V8_ARM_ASSEMBLER_ARM_H_ 1035 #endif // V8_ARM_ASSEMBLER_ARM_H_
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