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| 1 // Copyright 2006-2010 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are |
| 4 // met: |
| 5 // |
| 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided |
| 11 // with the distribution. |
| 12 // * Neither the name of Google Inc. nor the names of its |
| 13 // contributors may be used to endorse or promote products derived |
| 14 // from this software without specific prior written permission. |
| 15 // |
| 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 19 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 20 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 |
| 28 #ifndef V8_MIPS_CONSTANTS_H_ |
| 29 #define V8_MIPS_CONSTANTS_H_ |
| 30 |
| 31 #include "checks.h" |
| 32 |
| 33 // UNIMPLEMENTED_ macro for MIPS. |
| 34 #define UNIMPLEMENTED_MIPS() \ |
| 35 v8::internal::PrintF("%s, \tline %d: \tfunction %s not implemented. \n", \ |
| 36 __FILE__, __LINE__, __func__) |
| 37 #define UNSUPPORTED_MIPS() v8::internal::PrintF("Unsupported instruction.\n") |
| 38 |
| 39 |
| 40 // Defines constants and accessor classes to assemble, disassemble and |
| 41 // simulate MIPS32 instructions. |
| 42 // |
| 43 // See MIPS32 Architecture For Programmers |
| 44 // Volume II: The MIPS32 Instruction Set |
| 45 // Try www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf . |
| 46 // Else e quick Google search and you'll find it. |
| 47 |
| 48 namespace assembler { |
| 49 namespace mips { |
| 50 |
| 51 // ----------------------------------------------------------------------------- |
| 52 // Registers and FPURegister |
| 53 |
| 54 // Number of general purpose registers |
| 55 static const int kNumRegisters = 32; |
| 56 static const int kInvalidRegister = -1; |
| 57 |
| 58 // Number of registers with HI, LO, and pc. |
| 59 static const int kNumSimuRegisters = 35; |
| 60 |
| 61 // In the simulator, the PC register is simulated as the 34th register |
| 62 static const int kPCRegister = 34; |
| 63 |
| 64 // Number coprocessor registers |
| 65 static const int kNumFPURegister = 32; |
| 66 static const int kInvalidFPURegister = -1; |
| 67 |
| 68 // Helper functions for converting between register numbers and names. |
| 69 class Registers { |
| 70 public: |
| 71 // Return the name of the register. |
| 72 static const char* Name(int reg); |
| 73 |
| 74 // Lookup the register number for the name provided. |
| 75 static int Number(const char* name); |
| 76 |
| 77 struct RegisterAlias { |
| 78 int reg; |
| 79 const char *name; |
| 80 }; |
| 81 |
| 82 static const int32_t kMaxValue = 0x7fffffff; |
| 83 static const int32_t kMinValue = 0x80000000; |
| 84 |
| 85 private: |
| 86 |
| 87 static const char* names_[kNumSimuRegisters]; |
| 88 static const RegisterAlias aliases_[]; |
| 89 }; |
| 90 |
| 91 // Helper functions for converting between register numbers and names. |
| 92 class FPURegister { |
| 93 public: |
| 94 // Return the name of the register. |
| 95 static const char* Name(int reg); |
| 96 |
| 97 // Lookup the register number for the name provided. |
| 98 static int Number(const char* name); |
| 99 |
| 100 struct RegisterAlias { |
| 101 int creg; |
| 102 const char *name; |
| 103 }; |
| 104 |
| 105 private: |
| 106 |
| 107 static const char* names_[kNumFPURegister]; |
| 108 static const RegisterAlias aliases_[]; |
| 109 }; |
| 110 |
| 111 |
| 112 // ----------------------------------------------------------------------------- |
| 113 // Instructions encoding constants. |
| 114 |
| 115 // On MIPS all instructions are 32 bits. |
| 116 typedef int32_t Instr; |
| 117 |
| 118 typedef unsigned char byte_; |
| 119 |
| 120 // Special Software Interrupt codes when used in the presence of the ARM |
| 121 // simulator. |
| 122 enum SoftwareInterruptCodes { |
| 123 // transition to C code |
| 124 call_rt_redirected = 0xfffff |
| 125 }; |
| 126 |
| 127 // ----- Fields offset and length. |
| 128 static const int kOpcodeShift = 26; |
| 129 static const int kOpcodeBits = 6; |
| 130 static const int kRsShift = 21; |
| 131 static const int kRsBits = 5; |
| 132 static const int kRtShift = 16; |
| 133 static const int kRtBits = 5; |
| 134 static const int kRdShift = 11; |
| 135 static const int kRdBits = 5; |
| 136 static const int kSaShift = 6; |
| 137 static const int kSaBits = 5; |
| 138 static const int kFunctionShift = 0; |
| 139 static const int kFunctionBits = 6; |
| 140 |
| 141 static const int kImm16Shift = 0; |
| 142 static const int kImm16Bits = 16; |
| 143 static const int kImm26Shift = 0; |
| 144 static const int kImm26Bits = 26; |
| 145 |
| 146 static const int kFsShift = 11; |
| 147 static const int kFsBits = 5; |
| 148 static const int kFtShift = 16; |
| 149 static const int kFtBits = 5; |
| 150 |
| 151 // ----- Miscellianous useful masks. |
| 152 // Instruction bit masks |
| 153 static const int kOpcodeMask = ((1 << kOpcodeBits) - 1) << kOpcodeShift; |
| 154 static const int kImm16Mask = ((1 << kImm16Bits) - 1) << kImm16Shift; |
| 155 static const int kImm26Mask = ((1 << kImm26Bits) - 1) << kImm26Shift; |
| 156 static const int kRsFieldMask = ((1 << kRsBits) - 1) << kRsShift; |
| 157 static const int kRtFieldMask = ((1 << kRtBits) - 1) << kRtShift; |
| 158 static const int kRdFieldMask = ((1 << kRdBits) - 1) << kRdShift; |
| 159 static const int kSaFieldMask = ((1 << kSaBits) - 1) << kSaShift; |
| 160 static const int kFunctionFieldMask = |
| 161 ((1 << kFunctionBits) - 1) << kFunctionShift; |
| 162 // Misc masks |
| 163 static const int HIMask = 0xffff << 16; |
| 164 static const int LOMask = 0xffff; |
| 165 static const int signMask = 0x80000000; |
| 166 |
| 167 |
| 168 // ----- MIPS Opcodes and Function Fields |
| 169 // We use this presentation to stay close to the table representation in |
| 170 // MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set |
| 171 enum Opcode { |
| 172 SPECIAL = 0 << kOpcodeShift, |
| 173 REGIMM = 1 << kOpcodeShift, |
| 174 |
| 175 J = ((0 << 3) + 2) << kOpcodeShift, |
| 176 JAL = ((0 << 3) + 3) << kOpcodeShift, |
| 177 BEQ = ((0 << 3) + 4) << kOpcodeShift, |
| 178 BNE = ((0 << 3) + 5) << kOpcodeShift, |
| 179 BLEZ = ((0 << 3) + 6) << kOpcodeShift, |
| 180 BGTZ = ((0 << 3) + 7) << kOpcodeShift, |
| 181 |
| 182 ADDI = ((1 << 3) + 0) << kOpcodeShift, |
| 183 ADDIU = ((1 << 3) + 1) << kOpcodeShift, |
| 184 SLTI = ((1 << 3) + 2) << kOpcodeShift, |
| 185 SLTIU = ((1 << 3) + 3) << kOpcodeShift, |
| 186 ANDI = ((1 << 3) + 4) << kOpcodeShift, |
| 187 ORI = ((1 << 3) + 5) << kOpcodeShift, |
| 188 XORI = ((1 << 3) + 6) << kOpcodeShift, |
| 189 LUI = ((1 << 3) + 7) << kOpcodeShift, |
| 190 |
| 191 COP1 = ((2 << 3) + 1) << kOpcodeShift, // Coprocessor 1 class |
| 192 BEQL = ((2 << 3) + 4) << kOpcodeShift, |
| 193 BNEL = ((2 << 3) + 5) << kOpcodeShift, |
| 194 BLEZL = ((2 << 3) + 6) << kOpcodeShift, |
| 195 BGTZL = ((2 << 3) + 7) << kOpcodeShift, |
| 196 |
| 197 SPECIAL2 = ((3 << 3) + 4) << kOpcodeShift, |
| 198 |
| 199 LB = ((4 << 3) + 0) << kOpcodeShift, |
| 200 LW = ((4 << 3) + 3) << kOpcodeShift, |
| 201 LBU = ((4 << 3) + 4) << kOpcodeShift, |
| 202 SB = ((5 << 3) + 0) << kOpcodeShift, |
| 203 SW = ((5 << 3) + 3) << kOpcodeShift, |
| 204 |
| 205 LWC1 = ((6 << 3) + 1) << kOpcodeShift, |
| 206 LDC1 = ((6 << 3) + 5) << kOpcodeShift, |
| 207 |
| 208 SWC1 = ((7 << 3) + 1) << kOpcodeShift, |
| 209 SDC1 = ((7 << 3) + 5) << kOpcodeShift |
| 210 }; |
| 211 |
| 212 enum SecondaryField { |
| 213 // SPECIAL Encoding of Function Field |
| 214 SLL = ((0 << 3) + 0), |
| 215 SRL = ((0 << 3) + 2), |
| 216 SRA = ((0 << 3) + 3), |
| 217 SLLV = ((0 << 3) + 4), |
| 218 SRLV = ((0 << 3) + 6), |
| 219 SRAV = ((0 << 3) + 7), |
| 220 |
| 221 JR = ((1 << 3) + 0), |
| 222 JALR = ((1 << 3) + 1), |
| 223 BREAK = ((1 << 3) + 5), |
| 224 |
| 225 MFHI = ((2 << 3) + 0), |
| 226 MFLO = ((2 << 3) + 2), |
| 227 |
| 228 MULT = ((3 << 3) + 0), |
| 229 MULTU = ((3 << 3) + 1), |
| 230 DIV = ((3 << 3) + 2), |
| 231 DIVU = ((3 << 3) + 3), |
| 232 |
| 233 ADD = ((4 << 3) + 0), |
| 234 ADDU = ((4 << 3) + 1), |
| 235 SUB = ((4 << 3) + 2), |
| 236 SUBU = ((4 << 3) + 3), |
| 237 AND = ((4 << 3) + 4), |
| 238 OR = ((4 << 3) + 5), |
| 239 XOR = ((4 << 3) + 6), |
| 240 NOR = ((4 << 3) + 7), |
| 241 |
| 242 SLT = ((5 << 3) + 2), |
| 243 SLTU = ((5 << 3) + 3), |
| 244 |
| 245 TGE = ((6 << 3) + 0), |
| 246 TGEU = ((6 << 3) + 1), |
| 247 TLT = ((6 << 3) + 2), |
| 248 TLTU = ((6 << 3) + 3), |
| 249 TEQ = ((6 << 3) + 4), |
| 250 TNE = ((6 << 3) + 6), |
| 251 |
| 252 // SPECIAL2 Encoding of Function Field |
| 253 MUL = ((0 << 3) + 2), |
| 254 |
| 255 // REGIMM encoding of rt Field |
| 256 BLTZ = ((0 << 3) + 0) << 16, |
| 257 BGEZ = ((0 << 3) + 1) << 16, |
| 258 BLTZAL = ((2 << 3) + 0) << 16, |
| 259 BGEZAL = ((2 << 3) + 1) << 16, |
| 260 |
| 261 // COP1 Encoding of rs Field |
| 262 MFC1 = ((0 << 3) + 0) << 21, |
| 263 MFHC1 = ((0 << 3) + 3) << 21, |
| 264 MTC1 = ((0 << 3) + 4) << 21, |
| 265 MTHC1 = ((0 << 3) + 7) << 21, |
| 266 BC1 = ((1 << 3) + 0) << 21, |
| 267 S = ((2 << 3) + 0) << 21, |
| 268 D = ((2 << 3) + 1) << 21, |
| 269 W = ((2 << 3) + 4) << 21, |
| 270 L = ((2 << 3) + 5) << 21, |
| 271 PS = ((2 << 3) + 6) << 21, |
| 272 // COP1 Encoding of Function Field When rs=S |
| 273 CVT_D_S = ((4 << 3) + 1), |
| 274 CVT_W_S = ((4 << 3) + 4), |
| 275 CVT_L_S = ((4 << 3) + 5), |
| 276 CVT_PS_S = ((4 << 3) + 6), |
| 277 // COP1 Encoding of Function Field When rs=D |
| 278 CVT_S_D = ((4 << 3) + 0), |
| 279 CVT_W_D = ((4 << 3) + 4), |
| 280 CVT_L_D = ((4 << 3) + 5), |
| 281 // COP1 Encoding of Function Field When rs=W or L |
| 282 CVT_S_W = ((4 << 3) + 0), |
| 283 CVT_D_W = ((4 << 3) + 1), |
| 284 CVT_S_L = ((4 << 3) + 0), |
| 285 CVT_D_L = ((4 << 3) + 1), |
| 286 // COP1 Encoding of Function Field When rs=PS |
| 287 |
| 288 NULLSF = 0 |
| 289 }; |
| 290 |
| 291 |
| 292 // ----- Emulated conditions |
| 293 // On MIPS we use this enum to abstract from conditionnal branch instructions. |
| 294 // the 'U' prefix is used to specify unsigned comparisons. |
| 295 enum Condition { |
| 296 // any value < 0 is considered no_condition |
| 297 no_condition = -1, |
| 298 |
| 299 overflow = 0, |
| 300 no_overflow = 1, |
| 301 Uless = 2, |
| 302 Ugreater_equal= 3, |
| 303 equal = 4, |
| 304 not_equal = 5, |
| 305 Uless_equal = 6, |
| 306 Ugreater = 7, |
| 307 negative = 8, |
| 308 positive = 9, |
| 309 parity_even = 10, |
| 310 parity_odd = 11, |
| 311 less = 12, |
| 312 greater_equal = 13, |
| 313 less_equal = 14, |
| 314 greater = 15, |
| 315 |
| 316 cc_always = 16, |
| 317 |
| 318 // aliases |
| 319 carry = Uless, |
| 320 not_carry = Ugreater_equal, |
| 321 zero = equal, |
| 322 eq = equal, |
| 323 not_zero = not_equal, |
| 324 ne = not_equal, |
| 325 sign = negative, |
| 326 not_sign = positive, |
| 327 |
| 328 cc_default = no_condition |
| 329 }; |
| 330 |
| 331 // ----- Coprocessor conditions |
| 332 enum FPUCondition { |
| 333 F, // False |
| 334 UN, // Unordered |
| 335 EQ, // Equal |
| 336 UEQ, // Unordered or Equal |
| 337 OLT, // Ordered or Less Than |
| 338 ULT, // Unordered or Less Than |
| 339 OLE, // Ordered or Less Than or Equal |
| 340 ULE // Unordered or Less Than or Equal |
| 341 }; |
| 342 |
| 343 |
| 344 // break 0xfffff, reserved for redirected real time call |
| 345 const Instr rtCallRedirInstr = SPECIAL | BREAK | call_rt_redirected << 6; |
| 346 // A nop instruction. (Encoding of sll 0 0 0) |
| 347 const Instr nopInstr = 0; |
| 348 |
| 349 class Instruction { |
| 350 public: |
| 351 enum { |
| 352 kInstructionSize = 4, |
| 353 kInstructionSizeLog2 = 2, |
| 354 // On MIPS PC cannot actually be directly accessed. We behave as if PC was |
| 355 // always the value of the current instruction being exectued. |
| 356 kPCReadOffset = 0 |
| 357 }; |
| 358 |
| 359 // Get the raw instruction bits. |
| 360 inline Instr InstructionBits() const { |
| 361 return *reinterpret_cast<const Instr*>(this); |
| 362 } |
| 363 |
| 364 // Set the raw instruction bits to value. |
| 365 inline void SetInstructionBits(Instr value) { |
| 366 *reinterpret_cast<Instr*>(this) = value; |
| 367 } |
| 368 |
| 369 // Read one particular bit out of the instruction bits. |
| 370 inline int Bit(int nr) const { |
| 371 return (InstructionBits() >> nr) & 1; |
| 372 } |
| 373 |
| 374 // Read a bit field out of the instruction bits. |
| 375 inline int Bits(int hi, int lo) const { |
| 376 return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1); |
| 377 } |
| 378 |
| 379 // Instruction type. |
| 380 enum Type { |
| 381 kRegisterType, |
| 382 kImmediateType, |
| 383 kJumpType, |
| 384 kUnsupported = -1 |
| 385 }; |
| 386 |
| 387 // Get the encoding type of the instruction. |
| 388 Type InstructionType() const; |
| 389 |
| 390 |
| 391 // Accessors for the different named fields used in the MIPS encoding. |
| 392 // Generally applicable fields |
| 393 |
| 394 // Fields used in Data processing instructions |
| 395 inline Opcode OpcodeField() const { |
| 396 return static_cast<Opcode>( |
| 397 Bits(kOpcodeShift + kOpcodeBits - 1, kOpcodeShift)); |
| 398 } |
| 399 |
| 400 inline int RsField() const { |
| 401 ASSERT(InstructionType() == kRegisterType || |
| 402 InstructionType() == kImmediateType); |
| 403 return Bits(kRsShift + kRsBits - 1, kRsShift); |
| 404 } |
| 405 |
| 406 inline int RtField() const { |
| 407 ASSERT(InstructionType() == kRegisterType || |
| 408 InstructionType() == kImmediateType); |
| 409 return Bits(kRtShift + kRtBits - 1, kRtShift); |
| 410 } |
| 411 |
| 412 inline int RdField() const { |
| 413 ASSERT(InstructionType() == kRegisterType); |
| 414 return Bits(kRdShift + kRdBits - 1, kRdShift); |
| 415 } |
| 416 |
| 417 inline int SaField() const { |
| 418 ASSERT(InstructionType() == kRegisterType); |
| 419 return Bits(kSaShift + kSaBits - 1, kSaShift); |
| 420 } |
| 421 |
| 422 inline int FunctionField() const { |
| 423 ASSERT(InstructionType() == kRegisterType || |
| 424 InstructionType() == kImmediateType); |
| 425 return Bits(kFunctionShift + kFunctionBits - 1, kFunctionShift); |
| 426 } |
| 427 |
| 428 inline int FsField() const { |
| 429 return Bits(kFsShift + kRsBits - 1, kFsShift); |
| 430 } |
| 431 |
| 432 inline int FtField() const { |
| 433 return Bits(kFtShift + kRsBits - 1, kFtShift); |
| 434 } |
| 435 |
| 436 // Return the fields at their original place in the instruction encoding. |
| 437 inline Opcode OpcodeFieldRaw() const { |
| 438 return static_cast<Opcode>(InstructionBits() & kOpcodeMask); |
| 439 } |
| 440 |
| 441 inline int RsFieldRaw() const { |
| 442 ASSERT(InstructionType() == kRegisterType || |
| 443 InstructionType() == kImmediateType); |
| 444 return InstructionBits() & kRsFieldMask; |
| 445 } |
| 446 |
| 447 inline int RtFieldRaw() const { |
| 448 ASSERT(InstructionType() == kRegisterType || |
| 449 InstructionType() == kImmediateType); |
| 450 return InstructionBits() & kRtFieldMask; |
| 451 } |
| 452 |
| 453 inline int RdFieldRaw() const { |
| 454 ASSERT(InstructionType() == kRegisterType); |
| 455 return InstructionBits() & kRdFieldMask; |
| 456 } |
| 457 |
| 458 inline int SaFieldRaw() const { |
| 459 ASSERT(InstructionType() == kRegisterType); |
| 460 return InstructionBits() & kSaFieldMask; |
| 461 } |
| 462 |
| 463 inline int FunctionFieldRaw() const { |
| 464 return InstructionBits() & kFunctionFieldMask; |
| 465 } |
| 466 |
| 467 // Get the secondary field according to the opcode. |
| 468 inline int SecondaryField() const { |
| 469 Opcode op = OpcodeFieldRaw(); |
| 470 switch (op) { |
| 471 case SPECIAL: |
| 472 case SPECIAL2: |
| 473 return FunctionField(); |
| 474 case COP1: |
| 475 return RsField(); |
| 476 case REGIMM: |
| 477 return RtField(); |
| 478 default: |
| 479 return NULLSF; |
| 480 } |
| 481 } |
| 482 |
| 483 inline int32_t Imm16Field() const { |
| 484 ASSERT(InstructionType() == kImmediateType); |
| 485 return Bits(kImm16Shift + kImm16Bits - 1, kImm16Shift); |
| 486 } |
| 487 |
| 488 inline int32_t Imm26Field() const { |
| 489 ASSERT(InstructionType() == kJumpType); |
| 490 return Bits(kImm16Shift + kImm26Bits - 1, kImm26Shift); |
| 491 } |
| 492 |
| 493 // Say if the instruction should not be used in a branch delay slot. |
| 494 bool IsForbiddenInBranchDelay(); |
| 495 // Say if the instruction 'links'. eg: jal, bal |
| 496 bool IsLinkingInstruction(); |
| 497 // Say if the instruction is a break or a trap. |
| 498 bool IsTrap(); |
| 499 |
| 500 // Instructions are read of out a code stream. The only way to get a |
| 501 // reference to an instruction is to convert a pointer. There is no way |
| 502 // to allocate or create instances of class Instruction. |
| 503 // Use the At(pc) function to create references to Instruction. |
| 504 static Instruction* At(byte_* pc) { |
| 505 return reinterpret_cast<Instruction*>(pc); |
| 506 } |
| 507 |
| 508 private: |
| 509 // We need to prevent the creation of instances of class Instruction. |
| 510 DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction); |
| 511 }; |
| 512 |
| 513 |
| 514 // ----------------------------------------------------------------------------- |
| 515 // MIPS assembly various constants |
| 516 |
| 517 static const int kArgsSlotsSize = 4 * Instruction::kInstructionSize; |
| 518 static const int kArgsSlotsNum = 4; |
| 519 |
| 520 static const int kBranchReturnOffset = 2 * Instruction::kInstructionSize; |
| 521 |
| 522 static const int kDoubleAlignment = 2 * 8; |
| 523 static const int kDoubleAlignmentMask = kDoubleAlignmentMask - 1; |
| 524 |
| 525 |
| 526 } } // namespace assembler::mips |
| 527 |
| 528 #endif // #ifndef V8_MIPS_CONSTANTS_H_ |
| 529 |
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