OLD | NEW |
1 // Copyright 2010 the V8 project authors. All rights reserved. | 1 // Copyright 2010 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
(...skipping 1028 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1039 // vmov: Sn = Rt | 1039 // vmov: Sn = Rt |
1040 // vmov: Rt = Sn | 1040 // vmov: Rt = Sn |
1041 // vcvt: Dd = Sm | 1041 // vcvt: Dd = Sm |
1042 // vcvt: Sd = Dm | 1042 // vcvt: Sd = Dm |
1043 // Dd = vadd(Dn, Dm) | 1043 // Dd = vadd(Dn, Dm) |
1044 // Dd = vsub(Dn, Dm) | 1044 // Dd = vsub(Dn, Dm) |
1045 // Dd = vmul(Dn, Dm) | 1045 // Dd = vmul(Dn, Dm) |
1046 // Dd = vdiv(Dn, Dm) | 1046 // Dd = vdiv(Dn, Dm) |
1047 // vcmp(Dd, Dm) | 1047 // vcmp(Dd, Dm) |
1048 // vmrs | 1048 // vmrs |
| 1049 // vmsr |
1049 // Dd = vsqrt(Dm) | 1050 // Dd = vsqrt(Dm) |
1050 void Decoder::DecodeTypeVFP(Instr* instr) { | 1051 void Decoder::DecodeTypeVFP(Instr* instr) { |
1051 ASSERT((instr->TypeField() == 7) && (instr->Bit(24) == 0x0) ); | 1052 ASSERT((instr->TypeField() == 7) && (instr->Bit(24) == 0x0) ); |
1052 ASSERT(instr->Bits(11, 9) == 0x5); | 1053 ASSERT(instr->Bits(11, 9) == 0x5); |
1053 | 1054 |
1054 if (instr->Bit(4) == 0) { | 1055 if (instr->Bit(4) == 0) { |
1055 if (instr->Opc1Field() == 0x7) { | 1056 if (instr->Opc1Field() == 0x7) { |
1056 // Other data processing instructions | 1057 // Other data processing instructions |
1057 if ((instr->Opc2Field() == 0x0) && (instr->Opc3Field() == 0x1)) { | 1058 if ((instr->Opc2Field() == 0x0) && (instr->Opc3Field() == 0x1)) { |
1058 // vmov register to register. | 1059 // vmov register to register. |
(...skipping 45 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1104 } else { | 1105 } else { |
1105 Unknown(instr); // Not used by V8. | 1106 Unknown(instr); // Not used by V8. |
1106 } | 1107 } |
1107 } else { | 1108 } else { |
1108 Unknown(instr); // Not used by V8. | 1109 Unknown(instr); // Not used by V8. |
1109 } | 1110 } |
1110 } else { | 1111 } else { |
1111 if ((instr->VCField() == 0x0) && | 1112 if ((instr->VCField() == 0x0) && |
1112 (instr->VAField() == 0x0)) { | 1113 (instr->VAField() == 0x0)) { |
1113 DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(instr); | 1114 DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(instr); |
1114 } else if ((instr->VLField() == 0x1) && | 1115 } else if ((instr->VCField() == 0x0) && |
1115 (instr->VCField() == 0x0) && | |
1116 (instr->VAField() == 0x7) && | 1116 (instr->VAField() == 0x7) && |
1117 (instr->Bits(19, 16) == 0x1)) { | 1117 (instr->Bits(19, 16) == 0x1)) { |
1118 if (instr->Bits(15, 12) == 0xF) | 1118 if (instr->VLField() == 0) { |
1119 Format(instr, "vmrs'cond APSR, FPSCR"); | 1119 if (instr->Bits(15, 12) == 0xF) { |
1120 else | 1120 Format(instr, "vmsr'cond FPSCR, APSR"); |
1121 Unknown(instr); // Not used by V8. | 1121 } else { |
1122 } else { | 1122 Format(instr, "vmsr'cond FPSCR, 'rt"); |
1123 Unknown(instr); // Not used by V8. | 1123 } |
| 1124 } else { |
| 1125 if (instr->Bits(15, 12) == 0xF) { |
| 1126 Format(instr, "vmrs'cond APSR, FPSCR"); |
| 1127 } else { |
| 1128 Format(instr, "vmrs'cond 'rt, FPSCR"); |
| 1129 } |
| 1130 } |
1124 } | 1131 } |
1125 } | 1132 } |
1126 } | 1133 } |
1127 | 1134 |
1128 | 1135 |
1129 void Decoder::DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(Instr* instr) { | 1136 void Decoder::DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(Instr* instr) { |
1130 ASSERT((instr->Bit(4) == 1) && (instr->VCField() == 0x0) && | 1137 ASSERT((instr->Bit(4) == 1) && (instr->VCField() == 0x0) && |
1131 (instr->VAField() == 0x0)); | 1138 (instr->VAField() == 0x0)); |
1132 | 1139 |
1133 bool to_arm_register = (instr->VLField() == 0x1); | 1140 bool to_arm_register = (instr->VLField() == 0x1); |
(...skipping 285 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1419 pc += d.InstructionDecode(buffer, pc); | 1426 pc += d.InstructionDecode(buffer, pc); |
1420 fprintf(f, "%p %08x %s\n", | 1427 fprintf(f, "%p %08x %s\n", |
1421 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 1428 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
1422 } | 1429 } |
1423 } | 1430 } |
1424 | 1431 |
1425 | 1432 |
1426 } // namespace disasm | 1433 } // namespace disasm |
1427 | 1434 |
1428 #endif // V8_TARGET_ARCH_ARM | 1435 #endif // V8_TARGET_ARCH_ARM |
OLD | NEW |