include/configs/chromeos/tegra2/harmony/recovery.h - Issue 4841001: Tegra2: implement Warmboot code and lp0_vec

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Side by Side Diff: include/configs/chromeos/tegra2/harmony/recovery.h

Issue 4841001: Tegra2: implement Warmboot code and lp0_vec (Closed) Base URL: http://git.chromium.org/git/u-boot-next.git@chromeos-v2010.09

Patch Set: Add CONFIG_TEGRA2_LP0 to support LP0 conditionally Created 10 years, 1 month ago

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« board/tegra2/seaboard/Makefile ('K') | « include/configs/chromeos/tegra2/common.h ('k') | include/configs/chromeos/tegra2/seaboard/recovery.h » ('j') | include/configs/chromeos/tegra2/seaboard/recovery.h » ('J')
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1 /*	1 /*

2 * (C) Copyright 2010	2 * (C) Copyright 2010

3 * NVIDIA Corporation <www.nvidia.com>	3 * NVIDIA Corporation <www.nvidia.com>

4 *	4 *

5 * See file CREDITS for list of people who contributed to this	5 * See file CREDITS for list of people who contributed to this

6 * project.	6 * project.

7 *	7 *

8 * This program is free software; you can redistribute it and/or	8 * This program is free software; you can redistribute it and/or

9 * modify it under the terms of the GNU General Public License as	9 * modify it under the terms of the GNU General Public License as

10 * published by the Free Software Foundation; either version 2 of	10 * published by the Free Software Foundation; either version 2 of

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30 #define CONFIG_SERIAL_MULTI 1	30 #define CONFIG_SERIAL_MULTI 1

31 #define CONFIG_TEGRA2_ENABLE_UARTD 1	31 #define CONFIG_TEGRA2_ENABLE_UARTD 1

32 #define CONFIG_TEGRA2_ENALBE_UARTA 0	32 #define CONFIG_TEGRA2_ENALBE_UARTA 0

33	33

34 /* UARTD: keyboard satellite board uart, default */	34 /* UARTD: keyboard satellite board uart, default */

35 #define CONFIG_SYS_NS16550_COM1 NV_ADDRESS_MAP_APB_UARTD_BASE	35 #define CONFIG_SYS_NS16550_COM1 NV_ADDRESS_MAP_APB_UARTD_BASE

36	36

37 /* UARTA: debug board uart */	37 /* UARTA: debug board uart */

38 #define CONFIG_SYS_NS16550_COM2 NV_ADDRESS_MAP_APB_UARTA_BASE	38 #define CONFIG_SYS_NS16550_COM2 NV_ADDRESS_MAP_APB_UARTA_BASE

39	39

	40 #ifdef CONFIG_TEGRA2_LP0

	41 #define CONFIG_EXTRA_ENV_SETTINGS \

	42 CONFIG_TEGRA_ENV_SETTINGS \

	43 "platform_extras=mem=384M@0M nvmem=128M@384M mem=512M@512M "\

	44 "lp0_vec="TEGRA_LP0_SIZE_STR"@"TEGRA_LP0_DEFAULT_ADDR_STR "\0"

	45 #else

40 #define CONFIG_EXTRA_ENV_SETTINGS \	46 #define CONFIG_EXTRA_ENV_SETTINGS \

41 CONFIG_TEGRA_ENV_SETTINGS \	47 CONFIG_TEGRA_ENV_SETTINGS \

42 "platform_extras=mem=384M@0M nvmem=128M@384M mem=512M@512M\0"	48 "platform_extras=mem=384M@0M nvmem=128M@384M mem=512M@512M\0"

	49 #endif

43	50

44 #define LINUX_MACH_TYPE MACH_TYPE_HARMONY	51 #define LINUX_MACH_TYPE MACH_TYPE_HARMONY

45 #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 // lp1, 1GB	52 #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 // lp1, 1GB

46	53

47 #define CONFIG_SYS_MEMTEST_START 0x0000	54 #define CONFIG_SYS_MEMTEST_START 0x0000

48 #define CONFIG_SYS_MEMTEST_END 0x1000	55 #define CONFIG_SYS_MEMTEST_END 0x1000

49	56

50 #define CONFIG_I2CP_PIN_MUX 1	57 #define CONFIG_I2CP_PIN_MUX 1

51 #define CONFIG_I2C1_PIN_MUX 1	58 #define CONFIG_I2C1_PIN_MUX 1

52 #define CONFIG_I2C2_PIN_MUX 1	59 #define CONFIG_I2C2_PIN_MUX 1

53 #define CONFIG_I2C3_PIN_MUX 1	60 #define CONFIG_I2C3_PIN_MUX 1

54	61

55 #endif //__configs_chromeos_tegra2_harmony_recovery_h__	62 #endif //__configs_chromeos_tegra2_harmony_recovery_h__

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