Tegra2: implement Warmboot code and lp0_vec

arch/arm/cpu/arm_cortexa9/tegra2/ap20.h

 /*
  * (C) Copyright 2010
  * NVIDIA Corporation <www.nvidia.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
@@ skipping 13 matching lines @@
 #include <asm/arch/nvcommon.h>
 #include <asm/arch/nv_drf.h>
 #include <asm/arch/tegra2.h>
 #include <asm/arch/nv_hardware_access.h>
 #include <asm/arch/nvboot_bit.h>
 #include <asm/arch/nvboot_osc.h>
 #include <asm/arch/nvboot_clocks.h>
 #include <asm/arch/nvbl_memmap_nvap.h>
 #include <asm/arch/nvbl_arm_cpsr.h>
 #include <asm/arch/nvbl_arm_cp15.h>
+#include <asm/arch/nvboot_sdram_param.h>
 
 #define _AND_ &
 
 #define PG_UP_PA_BASE       0x60000000  // Base address for arpg.h registers
 #define PMC_PA_BASE         0x7000E400  // Base address for arapbpm.h registers
 #define CLK_RST_PA_BASE     0x60006000  // Base address for arclk_rst.h registers
 #define TIMERUS_PA_BASE     0x60005010  // Base address for artimerus.h registers
 #define FLOW_PA_BASE        0x60007000  // Base address for arflow_ctlr.h registers
 #define EMC_PA_BASE         0x7000f400  // Base address for aremc.h registers
 #define MC_PA_BASE          0x7000f000  // Base address for armc.h registers
 #define MISC_PA_BASE        0x70000000  // Base address for arapb_misc.h registers
 #define AHB_PA_BASE         0x6000C004  // Base address for arahb_arbc.h registers
 #define EVP_PA_BASE         0x6000F000  // Base address for arevp.h registers
 #define CSITE_PA_BASE       0x70040000  // Base address for arcsite.h registers
+#define ARM_PREF_BASE       0x50040000
 
 #define NV_PMC_REGR(pCar, reg)          NV_READ32( (((NvUPtr)(pCar)) + APBDEV_PMC_##reg##_0))
 #define NV_PMC_REGW(pCar, reg, val)     NV_WRITE32((((NvUPtr)(pCar)) + APBDEV_PMC_##reg##_0), (val))
 #define NV_FLOW_REGR(pFlow, reg)        NV_READ32((((NvUPtr)(pFlow)) + FLOW_CTLR_##reg##_0))
 #define NV_FLOW_REGW(pFlow, reg, val)   NV_WRITE32((((NvUPtr)(pFlow)) + FLOW_CTLR_##reg##_0), (val))
 #define NV_EVP_REGR(pEvp, reg)          NV_READ32( (((NvUPtr)(pEvp)) + EVP_##reg##_0))
 #define NV_EVP_REGW(pEvp, reg, val)     NV_WRITE32((((NvUPtr)(pEvp)) + EVP_##reg##_0), (val))
 
 #define USE_PLLC_OUT1               0       // 0 ==> PLLP_OUT4, 1 ==> PLLC_OUT1
 #define NVBL_PLL_BYPASS 0
@@ skipping 34 matching lines @@
 /// Calculate clock fractional divider value from reference and target frequencies
 #define CLK_DIVIDER(REF, FREQ)  ((((REF) * 2) / FREQ) - 2)
 
 /// Calculate clock frequency value from reference and clock divider value
 #define CLK_FREQUENCY(REF, REG)  (((REF) * 2) / (REG + 2))
 
 #define SCU_CONTROL_0                   _MK_ADDR_CONST(0x0)
 #define SCU_CONTROL_0_SCU_ENABLE_RANGE                  0:0
 #define SCU_INVALID_ALL_0                       _MK_ADDR_CONST(0xc)
 
-#define ARM_PREF_BASE  0x50040000
-
 #define NV_SCU_REGR(reg)      NV_READ32(ARM_PREF_BASE + SCU_##reg##_0)
 #define NV_SCU_REGW(reg, val) NV_WRITE32((ARM_PREF_BASE + SCU_##reg##_0), (val))
 
 //------------------------------------------------------------------------------
 // Provide missing enumerators for spec files.
 //------------------------------------------------------------------------------
 
 #define NV_BIT_ADDRESS 0x40000000
 #define NV3P_SIGNATURE 0x5AFEADD8
 
 void NvBlStartCpu_AP20(NvU32 ResetVector);
 void NvBlAvpHalt_AP20(void);
 NV_NAKED void NvBlStartUpAvp_AP20( void );
 NV_NAKED void ColdBoot_AP20( void );
 void tegra2_start(void);
 void uart_post(char c);
 void NvBlUartInit(void);
 void cpu_start(void);
 void cpu_init_crit(void);
 void PostZz(void);
 void PostYy(void);
 void PostXx(void);
+void NvBlPrintU32(NvU32);