Index: src/arm/disasm-arm.cc |
=================================================================== |
--- src/arm/disasm-arm.cc (revision 3427) |
+++ src/arm/disasm-arm.cc (working copy) |
@@ -897,15 +897,14 @@ |
// void Decoder::DecodeTypeVFP(Instr* instr) |
-// Implements the following VFP instructions: |
-// fmsr: Sn = Rt |
-// fmrs: Rt = Sn |
-// fsitod: Dd = Sm |
-// ftosid: Sd = Dm |
-// Dd = faddd(Dn, Dm) |
-// Dd = fsubd(Dn, Dm) |
-// Dd = fmuld(Dn, Dm) |
-// Dd = fdivd(Dn, Dm) |
+// vmov: Sn = Rt |
+// vmov: Rt = Sn |
+// vcvt: Dd = Sm |
+// vcvt: Sd = Dm |
+// Dd = vadd(Dn, Dm) |
+// Dd = vsub(Dn, Dm) |
+// Dd = vmul(Dn, Dm) |
+// Dd = vdiv(Dn, Dm) |
// vcmp(Dd, Dm) |
// VMRS |
void Decoder::DecodeTypeVFP(Instr* instr) { |
@@ -997,8 +996,8 @@ |
// Decode Type 6 coprocessor instructions. |
-// Dm = fmdrr(Rt, Rt2) |
-// <Rt, Rt2> = fmrrd(Dm) |
+// Dm = vmov(Rt, Rt2) |
+// <Rt, Rt2> = vmov(Dm) |
void Decoder::DecodeType6CoprocessorIns(Instr* instr) { |
ASSERT((instr->TypeField() == 6)); |