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Side by Side Diff: src/assembler-arm.h

Issue 42610: Fix and cleanup ARM port:... (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: Created 11 years, 9 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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215 215
216 // Branch hints are not used on the ARM. They are defined so that they can 216 // Branch hints are not used on the ARM. They are defined so that they can
217 // appear in shared function signatures, but will be ignored in ARM 217 // appear in shared function signatures, but will be ignored in ARM
218 // implementations. 218 // implementations.
219 enum Hint { no_hint }; 219 enum Hint { no_hint };
220 220
221 // Hints are not used on the arm. Negating is trivial. 221 // Hints are not used on the arm. Negating is trivial.
222 inline Hint NegateHint(Hint ignored) { return no_hint; } 222 inline Hint NegateHint(Hint ignored) { return no_hint; }
223 223
224 224
225 // The pc store offset may be 8 or 12 depending on the processor implementation.
226 int PcStoreOffset();
227
228
229 // ----------------------------------------------------------------------------- 225 // -----------------------------------------------------------------------------
230 // Addressing modes and instruction variants 226 // Addressing modes and instruction variants
231 227
232 // Shifter operand shift operation 228 // Shifter operand shift operation
233 enum ShiftOp { 229 enum ShiftOp {
234 LSL = 0 << 5, 230 LSL = 0 << 5,
235 LSR = 1 << 5, 231 LSR = 1 << 5,
236 ASR = 2 << 5, 232 ASR = 2 << 5,
237 ROR = 3 << 5, 233 ROR = 3 << 5,
238 RRX = -1 234 RRX = -1
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784 void link_to(Label* L, Label* appendix); 780 void link_to(Label* L, Label* appendix);
785 void next(Label* L); 781 void next(Label* L);
786 782
787 // Record reloc info for current pc_ 783 // Record reloc info for current pc_
788 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); 784 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
789 }; 785 };
790 786
791 } } // namespace v8::internal 787 } } // namespace v8::internal
792 788
793 #endif // V8_ASSEMBLER_ARM_H_ 789 #endif // V8_ASSEMBLER_ARM_H_
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