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| 1 // Copyright 2006-2009 the V8 project authors. All rights reserved. | 1 // Copyright 2006-2009 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
| 4 // met: | 4 // met: |
| 5 // | 5 // |
| 6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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| 213 | 213 |
| 214 void MacroAssembler::Move(Register dst, Register src) { | 214 void MacroAssembler::Move(Register dst, Register src) { |
| 215 if (!dst.is(src)) { | 215 if (!dst.is(src)) { |
| 216 mov(dst, src); | 216 mov(dst, src); |
| 217 } | 217 } |
| 218 } | 218 } |
| 219 | 219 |
| 220 | 220 |
| 221 void MacroAssembler::And(Register dst, Register src1, const Operand& src2, | 221 void MacroAssembler::And(Register dst, Register src1, const Operand& src2, |
| 222 Condition cond) { | 222 Condition cond) { |
| 223 if (!CpuFeatures::IsSupported(ARMv7) || src2.is_single_instruction()) { | 223 if (!src2.is_reg() && |
| 224 !src2.must_use_constant_pool() && |
| 225 src2.immediate() == 0) { |
| 226 mov(dst, Operand(0, RelocInfo::NONE), LeaveCC, cond); |
| 227 |
| 228 } else if (!src2.is_single_instruction() && |
| 229 !src2.must_use_constant_pool() && |
| 230 CpuFeatures::IsSupported(ARMv7) && |
| 231 IsPowerOf2(src2.immediate() + 1)) { |
| 232 ubfx(dst, src1, 0, WhichPowerOf2(src2.immediate() + 1), cond); |
| 233 |
| 234 } else { |
| 224 and_(dst, src1, src2, LeaveCC, cond); | 235 and_(dst, src1, src2, LeaveCC, cond); |
| 225 return; | |
| 226 } | 236 } |
| 227 int32_t immediate = src2.immediate(); | |
| 228 if (immediate == 0) { | |
| 229 mov(dst, Operand(0, RelocInfo::NONE), LeaveCC, cond); | |
| 230 return; | |
| 231 } | |
| 232 if (IsPowerOf2(immediate + 1) && ((immediate & 1) != 0)) { | |
| 233 ubfx(dst, src1, 0, WhichPowerOf2(immediate + 1), cond); | |
| 234 return; | |
| 235 } | |
| 236 and_(dst, src1, src2, LeaveCC, cond); | |
| 237 } | 237 } |
| 238 | 238 |
| 239 | 239 |
| 240 void MacroAssembler::Ubfx(Register dst, Register src1, int lsb, int width, | 240 void MacroAssembler::Ubfx(Register dst, Register src1, int lsb, int width, |
| 241 Condition cond) { | 241 Condition cond) { |
| 242 ASSERT(lsb < 32); | 242 ASSERT(lsb < 32); |
| 243 if (!CpuFeatures::IsSupported(ARMv7)) { | 243 if (!CpuFeatures::IsSupported(ARMv7)) { |
| 244 int mask = (1 << (width + lsb)) - 1 - ((1 << lsb) - 1); | 244 int mask = (1 << (width + lsb)) - 1 - ((1 << lsb) - 1); |
| 245 and_(dst, src1, Operand(mask), LeaveCC, cond); | 245 and_(dst, src1, Operand(mask), LeaveCC, cond); |
| 246 if (lsb != 0) { | 246 if (lsb != 0) { |
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| 1975 | 1975 |
| 1976 void CodePatcher::Emit(Address addr) { | 1976 void CodePatcher::Emit(Address addr) { |
| 1977 masm()->emit(reinterpret_cast<Instr>(addr)); | 1977 masm()->emit(reinterpret_cast<Instr>(addr)); |
| 1978 } | 1978 } |
| 1979 #endif // ENABLE_DEBUGGER_SUPPORT | 1979 #endif // ENABLE_DEBUGGER_SUPPORT |
| 1980 | 1980 |
| 1981 | 1981 |
| 1982 } } // namespace v8::internal | 1982 } } // namespace v8::internal |
| 1983 | 1983 |
| 1984 #endif // V8_TARGET_ARCH_ARM | 1984 #endif // V8_TARGET_ARCH_ARM |
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