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| 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 // All Rights Reserved. | 2 // All Rights Reserved. |
| 3 // | 3 // |
| 4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
| 5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
| 6 // are met: | 6 // are met: |
| 7 // | 7 // |
| 8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
| 9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
| 10 // | 10 // |
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| 441 | 441 |
| 442 // rm <shift_op> rs | 442 // rm <shift_op> rs |
| 443 explicit Operand(Register rm, ShiftOp shift_op, Register rs); | 443 explicit Operand(Register rm, ShiftOp shift_op, Register rs); |
| 444 | 444 |
| 445 // Return true if this is a register operand. | 445 // Return true if this is a register operand. |
| 446 INLINE(bool is_reg() const); | 446 INLINE(bool is_reg() const); |
| 447 | 447 |
| 448 // Return true of this operand fits in one instruction so that no | 448 // Return true of this operand fits in one instruction so that no |
| 449 // 2-instruction solution with a load into the ip register is necessary. | 449 // 2-instruction solution with a load into the ip register is necessary. |
| 450 bool is_single_instruction() const; | 450 bool is_single_instruction() const; |
| 451 bool must_use_constant_pool() const; |
| 451 | 452 |
| 452 inline int32_t immediate() const { | 453 inline int32_t immediate() const { |
| 453 ASSERT(!rm_.is_valid()); | 454 ASSERT(!rm_.is_valid()); |
| 454 return imm32_; | 455 return imm32_; |
| 455 } | 456 } |
| 456 | 457 |
| 457 Register rm() const { return rm_; } | 458 Register rm() const { return rm_; } |
| 458 Register rs() const { return rs_; } | 459 Register rs() const { return rs_; } |
| 459 ShiftOp shift_op() const { return shift_op_; } | 460 ShiftOp shift_op() const { return shift_op_; } |
| 460 | 461 |
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| 1291 public: | 1292 public: |
| 1292 EnsureSpace(Assembler* assembler) { | 1293 EnsureSpace(Assembler* assembler) { |
| 1293 assembler->CheckBuffer(); | 1294 assembler->CheckBuffer(); |
| 1294 } | 1295 } |
| 1295 }; | 1296 }; |
| 1296 | 1297 |
| 1297 | 1298 |
| 1298 } } // namespace v8::internal | 1299 } } // namespace v8::internal |
| 1299 | 1300 |
| 1300 #endif // V8_ARM_ASSEMBLER_ARM_H_ | 1301 #endif // V8_ARM_ASSEMBLER_ARM_H_ |
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