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Issue 42017: Fix issue 265 by handling extra statement state on the frame based on... (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: '' Created 11 years, 9 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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211 return cc; 211 return cc;
212 }; 212 };
213 } 213 }
214 214
215 215
216 // Branch hints are not used on the ARM. They are defined so that they can 216 // Branch hints are not used on the ARM. They are defined so that they can
217 // appear in shared function signatures, but will be ignored in ARM 217 // appear in shared function signatures, but will be ignored in ARM
218 // implementations. 218 // implementations.
219 enum Hint { no_hint }; 219 enum Hint { no_hint };
220 220
221 // Hints are not used on the arm. Negating is trivial.
222 inline Hint NegateHint(Hint ignored) { return no_hint; }
223
221 224
222 // The pc store offset may be 8 or 12 depending on the processor implementation. 225 // The pc store offset may be 8 or 12 depending on the processor implementation.
223 int PcStoreOffset(); 226 int PcStoreOffset();
224 227
225 228
226 // ----------------------------------------------------------------------------- 229 // -----------------------------------------------------------------------------
227 // Addressing modes and instruction variants 230 // Addressing modes and instruction variants
228 231
229 // Shifter operand shift operation 232 // Shifter operand shift operation
230 enum ShiftOp { 233 enum ShiftOp {
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781 void link_to(Label* L, Label* appendix); 784 void link_to(Label* L, Label* appendix);
782 void next(Label* L); 785 void next(Label* L);
783 786
784 // Record reloc info for current pc_ 787 // Record reloc info for current pc_
785 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); 788 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
786 }; 789 };
787 790
788 } } // namespace v8::internal 791 } } // namespace v8::internal
789 792
790 #endif // V8_ASSEMBLER_ARM_H_ 793 #endif // V8_ASSEMBLER_ARM_H_
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