OLD | NEW |
1 // Copyright 2007-2008 the V8 project authors. All rights reserved. | 1 // Copyright 2007-2008 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
(...skipping 254 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
265 ecx = 1, | 265 ecx = 1, |
266 edx = 2, | 266 edx = 2, |
267 ebx = 3, | 267 ebx = 3, |
268 esp = 4, | 268 esp = 4, |
269 ebp = 5, | 269 ebp = 5, |
270 esi = 6, | 270 esi = 6, |
271 edi = 7 | 271 edi = 7 |
272 }; | 272 }; |
273 | 273 |
274 | 274 |
| 275 enum ShiftOpcodeExtension { |
| 276 kROL = 0, |
| 277 kROR = 1, |
| 278 kRCL = 2, |
| 279 kRCR = 3, |
| 280 kSHL = 4, |
| 281 KSHR = 5, |
| 282 kSAR = 7 |
| 283 }; |
| 284 |
| 285 |
275 const char* NameOfCPURegister(int reg) const { | 286 const char* NameOfCPURegister(int reg) const { |
276 return converter_.NameOfCPURegister(reg); | 287 return converter_.NameOfCPURegister(reg); |
277 } | 288 } |
278 | 289 |
279 | 290 |
280 const char* NameOfByteCPURegister(int reg) const { | 291 const char* NameOfByteCPURegister(int reg) const { |
281 return converter_.NameOfByteCPURegister(reg); | 292 return converter_.NameOfByteCPURegister(reg); |
282 } | 293 } |
283 | 294 |
284 | 295 |
(...skipping 244 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
529 int DisassemblerIA32::D1D3C1Instruction(byte* data) { | 540 int DisassemblerIA32::D1D3C1Instruction(byte* data) { |
530 byte op = *data; | 541 byte op = *data; |
531 ASSERT(op == 0xD1 || op == 0xD3 || op == 0xC1); | 542 ASSERT(op == 0xD1 || op == 0xD3 || op == 0xC1); |
532 byte modrm = *(data+1); | 543 byte modrm = *(data+1); |
533 int mod, regop, rm; | 544 int mod, regop, rm; |
534 get_modrm(modrm, &mod, ®op, &rm); | 545 get_modrm(modrm, &mod, ®op, &rm); |
535 int imm8 = -1; | 546 int imm8 = -1; |
536 int num_bytes = 2; | 547 int num_bytes = 2; |
537 if (mod == 3) { | 548 if (mod == 3) { |
538 const char* mnem = NULL; | 549 const char* mnem = NULL; |
| 550 switch (regop) { |
| 551 case kROL: mnem = "rol"; break; |
| 552 case kROR: mnem = "ror"; break; |
| 553 case kRCL: mnem = "rcl"; break; |
| 554 case kSHL: mnem = "shl"; break; |
| 555 case KSHR: mnem = "shr"; break; |
| 556 case kSAR: mnem = "sar"; break; |
| 557 default: UnimplementedInstruction(); |
| 558 } |
539 if (op == 0xD1) { | 559 if (op == 0xD1) { |
540 imm8 = 1; | 560 imm8 = 1; |
541 switch (regop) { | |
542 case edx: mnem = "rcl"; break; | |
543 case edi: mnem = "sar"; break; | |
544 case esp: mnem = "shl"; break; | |
545 default: UnimplementedInstruction(); | |
546 } | |
547 } else if (op == 0xC1) { | 561 } else if (op == 0xC1) { |
548 imm8 = *(data+2); | 562 imm8 = *(data+2); |
549 num_bytes = 3; | 563 num_bytes = 3; |
550 switch (regop) { | |
551 case edx: mnem = "rcl"; break; | |
552 case esp: mnem = "shl"; break; | |
553 case ebp: mnem = "shr"; break; | |
554 case edi: mnem = "sar"; break; | |
555 default: UnimplementedInstruction(); | |
556 } | |
557 } else if (op == 0xD3) { | 564 } else if (op == 0xD3) { |
558 switch (regop) { | 565 // Shift/rotate by cl. |
559 case esp: mnem = "shl"; break; | |
560 case ebp: mnem = "shr"; break; | |
561 case edi: mnem = "sar"; break; | |
562 default: UnimplementedInstruction(); | |
563 } | |
564 } | 566 } |
565 ASSERT_NE(NULL, mnem); | 567 ASSERT_NE(NULL, mnem); |
566 AppendToBuffer("%s %s,", mnem, NameOfCPURegister(rm)); | 568 AppendToBuffer("%s %s,", mnem, NameOfCPURegister(rm)); |
567 if (imm8 > 0) { | 569 if (imm8 > 0) { |
568 AppendToBuffer("%d", imm8); | 570 AppendToBuffer("%d", imm8); |
569 } else { | 571 } else { |
570 AppendToBuffer("cl"); | 572 AppendToBuffer("cl"); |
571 } | 573 } |
572 } else { | 574 } else { |
573 UnimplementedInstruction(); | 575 UnimplementedInstruction(); |
(...skipping 713 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1287 } | 1289 } |
1288 for (int i = 6 - (pc - prev_pc); i >= 0; i--) { | 1290 for (int i = 6 - (pc - prev_pc); i >= 0; i--) { |
1289 fprintf(f, " "); | 1291 fprintf(f, " "); |
1290 } | 1292 } |
1291 fprintf(f, " %s\n", buffer.start()); | 1293 fprintf(f, " %s\n", buffer.start()); |
1292 } | 1294 } |
1293 } | 1295 } |
1294 | 1296 |
1295 | 1297 |
1296 } // namespace disasm | 1298 } // namespace disasm |
OLD | NEW |