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1 //------------------------------------------------------------------------------ | 1 //------------------------------------------------------------------------------ |
2 // <copyright file="common_drv.c" company="Atheros"> | 2 // <copyright file="common_drv.c" company="Atheros"> |
3 // Copyright (c) 2004-2008 Atheros Corporation. All rights reserved. | 3 // Copyright (c) 2004-2010 Atheros Corporation. All rights reserved. |
4 // | 4 // |
5 // This program is free software; you can redistribute it and/or modify | |
6 // it under the terms of the GNU General Public License version 2 as | |
7 // published by the Free Software Foundation; | |
8 // | 5 // |
9 // Software distributed under the License is distributed on an "AS | 6 // Permission to use, copy, modify, and/or distribute this software for any |
10 // IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | 7 // purpose with or without fee is hereby granted, provided that the above |
11 // implied. See the License for the specific language governing | 8 // copyright notice and this permission notice appear in all copies. |
12 // rights and limitations under the License. | 9 // |
| 10 // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 11 // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 12 // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 13 // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 14 // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 15 // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 16 // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
13 // | 17 // |
14 // | 18 // |
15 //------------------------------------------------------------------------------ | 19 //------------------------------------------------------------------------------ |
16 //============================================================================== | 20 //============================================================================== |
17 // Author(s): ="Atheros" | 21 // Author(s): ="Atheros" |
18 //============================================================================== | 22 //============================================================================== |
19 | 23 |
20 #include "a_config.h" | 24 #include "a_config.h" |
21 #include "athdefs.h" | 25 #include "athdefs.h" |
22 #include "a_types.h" | 26 #include "a_types.h" |
23 | 27 |
24 #include "AR6002/hw/mbox_host_reg.h" | 28 #include "AR6002/hw2.0/hw/mbox_host_reg.h" |
25 #include "AR6002/hw/apb_map.h" | 29 #include "AR6002/hw2.0/hw/apb_map.h" |
26 #include "AR6002/hw/si_reg.h" | 30 #include "AR6002/hw2.0/hw/si_reg.h" |
27 #include "AR6002/hw/gpio_reg.h" | 31 #include "AR6002/hw2.0/hw/gpio_reg.h" |
28 #include "AR6002/hw/rtc_reg.h" | 32 #include "AR6002/hw2.0/hw/rtc_reg.h" |
29 #include "AR6002/hw/vmc_reg.h" | 33 #include "AR6002/hw2.0/hw/vmc_reg.h" |
30 #include "AR6002/hw/mbox_reg.h" | 34 #include "AR6002/hw2.0/hw/mbox_reg.h" |
31 | 35 |
| 36 #include "a_osapi.h" |
32 #include "targaddrs.h" | 37 #include "targaddrs.h" |
33 #include "a_osapi.h" | |
34 #include "hif.h" | 38 #include "hif.h" |
35 #include "htc_api.h" | 39 #include "htc_api.h" |
36 #include "wmi.h" | 40 #include "wmi.h" |
37 #include "bmi.h" | 41 #include "bmi.h" |
38 #include "bmi_msg.h" | 42 #include "bmi_msg.h" |
39 #include "common_drv.h" | 43 #include "common_drv.h" |
40 #define ATH_MODULE_NAME misc | 44 #define ATH_MODULE_NAME misc |
41 #include "a_debug.h" | 45 #include "a_debug.h" |
42 #include "ar6000_diag.h" | 46 #include "ar6000_diag.h" |
43 | 47 |
44 static ATH_DEBUG_MODULE_DBG_INFO *g_pModuleInfoHead = NULL; | 48 static ATH_DEBUG_MODULE_DBG_INFO *g_pModuleInfoHead = NULL; |
45 static A_MUTEX_T g_ModuleListLock; | 49 static A_MUTEX_T g_ModuleListLock; |
46 static A_BOOL g_ModuleDebugInit = FALSE; | 50 static A_BOOL g_ModuleDebugInit = FALSE; |
47 | 51 |
48 #ifdef DEBUG | 52 #ifdef ATH_DEBUG_MODULE |
49 | 53 |
50 ATH_DEBUG_INSTANTIATE_MODULE_VAR(misc, | 54 ATH_DEBUG_INSTANTIATE_MODULE_VAR(misc, |
51 "misc", | 55 "misc", |
52 "Common and misc APIs", | 56 "Common and misc APIs", |
53 ATH_DEBUG_MASK_DEFAULTS, | 57 ATH_DEBUG_MASK_DEFAULTS, |
54 0, | 58 0, |
55 NULL); | 59 NULL); |
56 | 60 |
57 #endif | 61 #endif |
58 | 62 |
59 #define HOST_INTEREST_ITEM_ADDRESS(target, item) \ | 63 #define HOST_INTEREST_ITEM_ADDRESS(target, item) \ |
60 (((target) == TARGET_TYPE_AR6001) ? AR6001_HOST_INTEREST_ITEM_ADDRESS(it
em) : \ | 64 ((((target) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(i
tem) : \ |
61 (((target) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(it
em) : \ | 65 (((target) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(i
tem) : 0))) |
62 (((target) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(it
em) : 0))) | |
63 | 66 |
64 | 67 |
65 #define AR6001_LOCAL_COUNT_ADDRESS 0x0c014080 | 68 #define AR6001_LOCAL_COUNT_ADDRESS 0x0c014080 |
66 #define AR6002_LOCAL_COUNT_ADDRESS 0x00018080 | 69 #define AR6002_LOCAL_COUNT_ADDRESS 0x00018080 |
67 #define AR6003_LOCAL_COUNT_ADDRESS 0x00018080 | 70 #define AR6003_LOCAL_COUNT_ADDRESS 0x00018080 |
68 #define CPU_DBG_SEL_ADDRESS 0x00000483 | 71 #define CPU_DBG_SEL_ADDRESS 0x00000483 |
69 #define CPU_DBG_ADDRESS 0x00000484 | 72 #define CPU_DBG_ADDRESS 0x00000484 |
70 | 73 |
71 static A_UINT8 custDataAR6002[AR6002_CUST_DATA_SIZE]; | 74 static A_UINT8 custDataAR6002[AR6002_CUST_DATA_SIZE]; |
72 static A_UINT8 custDataAR6003[AR6003_CUST_DATA_SIZE]; | 75 static A_UINT8 custDataAR6003[AR6003_CUST_DATA_SIZE]; |
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357 static A_STATUS | 360 static A_STATUS |
358 _delay_until_target_alive(HIF_DEVICE *hifDevice, A_INT32 wait_msecs, A_UINT32 Ta
rgetType) | 361 _delay_until_target_alive(HIF_DEVICE *hifDevice, A_INT32 wait_msecs, A_UINT32 Ta
rgetType) |
359 { | 362 { |
360 A_INT32 actual_wait; | 363 A_INT32 actual_wait; |
361 A_INT32 i; | 364 A_INT32 i; |
362 A_UINT32 address; | 365 A_UINT32 address; |
363 | 366 |
364 actual_wait = 0; | 367 actual_wait = 0; |
365 | 368 |
366 /* Hardcode the address of LOCAL_COUNT_ADDRESS based on the target type */ | 369 /* Hardcode the address of LOCAL_COUNT_ADDRESS based on the target type */ |
367 if (TargetType == TARGET_TYPE_AR6001) { | 370 if (TargetType == TARGET_TYPE_AR6002) { |
368 address = AR6001_LOCAL_COUNT_ADDRESS; | |
369 } else if (TargetType == TARGET_TYPE_AR6002) { | |
370 address = AR6002_LOCAL_COUNT_ADDRESS; | 371 address = AR6002_LOCAL_COUNT_ADDRESS; |
371 } else if (TargetType == TARGET_TYPE_AR6003) { | 372 } else if (TargetType == TARGET_TYPE_AR6003) { |
372 address = AR6003_LOCAL_COUNT_ADDRESS; | 373 address = AR6003_LOCAL_COUNT_ADDRESS; |
373 } else { | 374 } else { |
374 A_ASSERT(0); | 375 A_ASSERT(0); |
375 } | 376 } |
376 address += 0x10; | 377 address += 0x10; |
377 for (i=0; actual_wait < wait_msecs; i++) { | 378 for (i=0; actual_wait < wait_msecs; i++) { |
378 A_UINT32 data; | 379 A_UINT32 data; |
379 | 380 |
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409 // address = RESET_CONTROL_ADDRESS; | 410 // address = RESET_CONTROL_ADDRESS; |
410 | 411 |
411 if (coldReset) { | 412 if (coldReset) { |
412 data = RESET_CONTROL_COLD_RST_MASK; | 413 data = RESET_CONTROL_COLD_RST_MASK; |
413 } | 414 } |
414 else { | 415 else { |
415 data = RESET_CONTROL_MBOX_RST_MASK; | 416 data = RESET_CONTROL_MBOX_RST_MASK; |
416 } | 417 } |
417 | 418 |
418 /* Hardcode the address of RESET_CONTROL_ADDRESS based on the target t
ype */ | 419 /* Hardcode the address of RESET_CONTROL_ADDRESS based on the target t
ype */ |
419 if (TargetType == TARGET_TYPE_AR6001) { | 420 if (TargetType == TARGET_TYPE_AR6002) { |
420 address = AR6001_RESET_CONTROL_ADDRESS; | |
421 } else if (TargetType == TARGET_TYPE_AR6002) { | |
422 address = AR6002_RESET_CONTROL_ADDRESS; | 421 address = AR6002_RESET_CONTROL_ADDRESS; |
423 } else if (TargetType == TARGET_TYPE_AR6003) { | 422 } else if (TargetType == TARGET_TYPE_AR6003) { |
424 address = AR6003_RESET_CONTROL_ADDRESS; | 423 address = AR6003_RESET_CONTROL_ADDRESS; |
425 } else { | 424 } else { |
426 A_ASSERT(0); | 425 A_ASSERT(0); |
427 } | 426 } |
428 | 427 |
429 | 428 |
430 status = ar6000_WriteRegDiag(hifDevice, &address, &data); | 429 status = ar6000_WriteRegDiag(hifDevice, &address, &data); |
431 | 430 |
432 if (A_FAILED(status)) { | 431 if (A_FAILED(status)) { |
433 break; | 432 break; |
434 } | 433 } |
435 | 434 |
436 if (!waitForCompletion) { | 435 if (!waitForCompletion) { |
437 break; | 436 break; |
438 } | 437 } |
439 | 438 |
440 #if 0 | 439 #if 0 |
441 /* Up to 2 second delay to allow things to settle down */ | 440 /* Up to 2 second delay to allow things to settle down */ |
442 (void)_delay_until_target_alive(hifDevice, 2000, TargetType); | 441 (void)_delay_until_target_alive(hifDevice, 2000, TargetType); |
443 | 442 |
444 /* | 443 /* |
445 * Read back the RESET CAUSE register to ensure that the cold reset | 444 * Read back the RESET CAUSE register to ensure that the cold reset |
446 * went through. | 445 * went through. |
447 */ | 446 */ |
448 | 447 |
449 // address = RESET_CAUSE_ADDRESS; | 448 // address = RESET_CAUSE_ADDRESS; |
450 /* Hardcode the address of RESET_CAUSE_ADDRESS based on the target type
*/ | 449 /* Hardcode the address of RESET_CAUSE_ADDRESS based on the target type
*/ |
451 if (TargetType == TARGET_TYPE_AR6001) { | 450 if (TargetType == TARGET_TYPE_AR6002) { |
452 address = 0x0C0000CC; | |
453 } else if (TargetType == TARGET_TYPE_AR6002) { | |
454 address = 0x000040C0; | 451 address = 0x000040C0; |
455 } else if (TargetType == TARGET_TYPE_AR6003) { | 452 } else if (TargetType == TARGET_TYPE_AR6003) { |
456 address = 0x000040C0; | 453 address = 0x000040C0; |
457 } else { | 454 } else { |
458 A_ASSERT(0); | 455 A_ASSERT(0); |
459 } | 456 } |
460 | 457 |
461 data = 0; | 458 data = 0; |
462 status = ar6000_ReadRegDiag(hifDevice, &address, &data); | 459 status = ar6000_ReadRegDiag(hifDevice, &address, &data); |
463 | 460 |
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564 A_UINT32 regDumpValues[REGISTER_DUMP_LEN_MAX]; | 561 A_UINT32 regDumpValues[REGISTER_DUMP_LEN_MAX]; |
565 A_UINT32 regDumpCount = 0; | 562 A_UINT32 regDumpCount = 0; |
566 A_UINT32 i; | 563 A_UINT32 i; |
567 | 564 |
568 do { | 565 do { |
569 | 566 |
570 /* the reg dump pointer is copied to the host interest area */ | 567 /* the reg dump pointer is copied to the host interest area */ |
571 address = HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_failure_state); | 568 address = HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_failure_state); |
572 address = TARG_VTOP(TargetType, address); | 569 address = TARG_VTOP(TargetType, address); |
573 | 570 |
574 if (TargetType == TARGET_TYPE_AR6001) { | 571 if (TargetType == TARGET_TYPE_AR6002) { |
575 /* for AR6001, this is a fixed location because the ptr is actua
lly stuck in cache, | |
576 * this may be fixed in later firmware versions */ | |
577 address = 0x18a0; | |
578 regDumpCount = REG_DUMP_COUNT_AR6001; | |
579 } else if (TargetType == TARGET_TYPE_AR6002) { | |
580 regDumpCount = REG_DUMP_COUNT_AR6002; | 572 regDumpCount = REG_DUMP_COUNT_AR6002; |
581 } else if (TargetType == TARGET_TYPE_AR6003) { | 573 } else if (TargetType == TARGET_TYPE_AR6003) { |
582 regDumpCount = REG_DUMP_COUNT_AR6003; | 574 regDumpCount = REG_DUMP_COUNT_AR6003; |
583 } else { | 575 } else { |
584 A_ASSERT(0); | 576 A_ASSERT(0); |
585 } | 577 } |
586 | 578 |
587 /* read RAM location through diagnostic window */ | 579 /* read RAM location through diagnostic window */ |
588 status = ar6000_ReadRegDiag(hifDevice, &address, ®DumpArea); | 580 status = ar6000_ReadRegDiag(hifDevice, &address, ®DumpArea); |
589 | 581 |
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1026 HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_hci_br
idge_flags), | 1018 HOST_INTEREST_ITEM_ADDRESS(TargetType, hi_hci_br
idge_flags), |
1027 (A_UCHAR *)&Flags, | 1019 (A_UCHAR *)&Flags, |
1028 4); | 1020 4); |
1029 | 1021 |
1030 | 1022 |
1031 } while (FALSE); | 1023 } while (FALSE); |
1032 | 1024 |
1033 return status; | 1025 return status; |
1034 } | 1026 } |
1035 | 1027 |
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