ath6kl: Bringing in the upstream version

chromeos/drivers/ath6kl/include/target_reg_table.h

 //------------------------------------------------------------------------------
 // <copyright file="target_reg_table.h" company="Atheros">
-//    Copyright (c) 2004-2008 Atheros Corporation.  All rights reserved.
+//    Copyright (c) 2004-2010 Atheros Corporation.  All rights reserved.
 // 
-// This program is free software; you can redistribute it and/or modify
-// it under the terms of the GNU General Public License version 2 as
-// published by the Free Software Foundation;
 //
-// Software distributed under the License is distributed on an "AS
-// IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
-// implied. See the License for the specific language governing
-// rights and limitations under the License.
+// Permission to use, copy, modify, and/or distribute this software for any
+// purpose with or without fee is hereby granted, provided that the above
+// copyright notice and this permission notice appear in all copies.
+//
+// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 //
 //
 //------------------------------------------------------------------------------
 //==============================================================================
 // Target register table macros and structure definitions
 //
 // Author(s): ="Atheros"
 //==============================================================================
 
 #ifndef TARGET_REG_TABLE_H_
@@ skipping 37 matching lines @@
     A_UINT32 d_SI_CS_OFFSET;
     A_UINT32 d_SI_CS_DONE_ERR_MASK;
     A_UINT32 d_SI_CS_DONE_INT_MASK;
     A_UINT32 d_SI_CS_START_LSB;
     A_UINT32 d_SI_CS_START_MASK;
     A_UINT32 d_SI_CS_RX_CNT_LSB;
     A_UINT32 d_SI_CS_RX_CNT_MASK;
     A_UINT32 d_SI_CS_TX_CNT_LSB;
     A_UINT32 d_SI_CS_TX_CNT_MASK;
     A_UINT32 d_BOARD_DATA_SZ;
+    A_UINT32 d_BOARD_EXT_DATA_SZ;
 } TARGET_REGISTER_TABLE;
 
 #define BOARD_DATA_SZ_MAX 2048
 
 #if defined(MY_TARGET_DEF) /* { */
 
 #ifdef ATH_REG_TABLE_DIRECT_ASSIGN
 
 static struct targetdef_s my_target_def = {
     RTC_BASE_ADDRESS,
@@ skipping 30 matching lines @@
     SI_CS_OFFSET,
     SI_CS_DONE_ERR_MASK,
     SI_CS_DONE_INT_MASK,
     SI_CS_START_LSB,
     SI_CS_START_MASK,
     SI_CS_RX_CNT_LSB,
     SI_CS_RX_CNT_MASK,
     SI_CS_TX_CNT_LSB,
     SI_CS_TX_CNT_MASK,
     MY_TARGET_BOARD_DATA_SZ,
+    MY_TARGET_BOARD_EXT_DATA_SZ,
 };
 
 #else
 
 static struct targetdef_s my_target_def = {
     .d_RTC_BASE_ADDRESS = RTC_BASE_ADDRESS,
     .d_SYSTEM_SLEEP_OFFSET = SYSTEM_SLEEP_OFFSET,
     .d_SYSTEM_SLEEP_DISABLE_LSB = SYSTEM_SLEEP_DISABLE_LSB,
     .d_SYSTEM_SLEEP_DISABLE_MASK = SYSTEM_SLEEP_DISABLE_MASK,
     .d_CLOCK_CONTROL_OFFSET = CLOCK_CONTROL_OFFSET,
@@ skipping 26 matching lines @@
     .d_SI_CS_OFFSET = SI_CS_OFFSET,
     .d_SI_CS_DONE_ERR_MASK = SI_CS_DONE_ERR_MASK,
     .d_SI_CS_DONE_INT_MASK = SI_CS_DONE_INT_MASK,
     .d_SI_CS_START_LSB = SI_CS_START_LSB,
     .d_SI_CS_START_MASK = SI_CS_START_MASK,
     .d_SI_CS_RX_CNT_LSB = SI_CS_RX_CNT_LSB,
     .d_SI_CS_RX_CNT_MASK = SI_CS_RX_CNT_MASK,
     .d_SI_CS_TX_CNT_LSB = SI_CS_TX_CNT_LSB,
     .d_SI_CS_TX_CNT_MASK = SI_CS_TX_CNT_MASK,
     .d_BOARD_DATA_SZ = MY_TARGET_BOARD_DATA_SZ,
+    .d_BOARD_EXT_DATA_SZ = MY_TARGET_BOARD_EXT_DATA_SZ,
 };
 
 #endif
 
 #if MY_TARGET_BOARD_DATA_SZ > BOARD_DATA_SZ_MAX
 #error "BOARD_DATA_SZ_MAX is too small"
 #endif
 
 struct targetdef_s *MY_TARGET_DEF = &my_target_def;
 
@@ skipping 33 matching lines @@
 #define SI_CS_OFFSET (targetdef->d_SI_CS_OFFSET)
 #define SI_CS_DONE_ERR_MASK (targetdef->d_SI_CS_DONE_ERR_MASK)
 #define SI_CS_DONE_INT_MASK (targetdef->d_SI_CS_DONE_INT_MASK)
 #define SI_CS_START_LSB (targetdef->d_SI_CS_START_LSB)
 #define SI_CS_START_MASK (targetdef->d_SI_CS_START_MASK)
 #define SI_CS_RX_CNT_LSB (targetdef->d_SI_CS_RX_CNT_LSB)
 #define SI_CS_RX_CNT_MASK (targetdef->d_SI_CS_RX_CNT_MASK)
 #define SI_CS_TX_CNT_LSB (targetdef->d_SI_CS_TX_CNT_LSB)
 #define SI_CS_TX_CNT_MASK (targetdef->d_SI_CS_TX_CNT_MASK)
 #define EEPROM_SZ (targetdef->d_BOARD_DATA_SZ)
+#define EEPROM_EXT_SZ (targetdef->d_BOARD_EXT_DATA_SZ)
 
 /* SET macros */
 #define SYSTEM_SLEEP_DISABLE_SET(x)              (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK)
 #define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
 #define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
 #define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
 #define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
 #define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
 #define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
 #define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
 #define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
 #define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
 
 #endif /* } */
 
 #endif /*TARGET_REG_TABLE_H_*/