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| 1 // ------------------------------------------------------------------ | |
| 2 // Copyright (c) 2004-2007 Atheros Corporation. All rights reserved. | |
| 3 // | |
| 4 // This program is free software; you can redistribute it and/or modify | |
| 5 // it under the terms of the GNU General Public License version 2 as | |
| 6 // published by the Free Software Foundation; | |
| 7 // | |
| 8 // Software distributed under the License is distributed on an "AS | |
| 9 // IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or | |
| 10 // implied. See the License for the specific language governing | |
| 11 // rights and limitations under the License. | |
| 12 // | |
| 13 // | |
| 14 // ------------------------------------------------------------------ | |
| 15 //=================================================================== | |
| 16 // Author(s): ="Atheros" | |
| 17 //=================================================================== | |
| 18 | |
| 19 | |
| 20 #ifndef _RTC_REG_REG_H_ | 1 #ifndef _RTC_REG_REG_H_ |
| 21 #define _RTC_REG_REG_H_ | 2 #define _RTC_REG_REG_H_ |
| 22 | 3 |
| 23 #define RESET_CONTROL_ADDRESS 0x00000000 | 4 #define RESET_CONTROL_ADDRESS 0x00000000 |
| 24 #define RESET_CONTROL_OFFSET 0x00000000 | 5 #define RESET_CONTROL_OFFSET 0x00000000 |
| 25 #define RESET_CONTROL_CPU_INIT_RESET_MSB 11 | 6 #define RESET_CONTROL_CPU_INIT_RESET_MSB 11 |
| 26 #define RESET_CONTROL_CPU_INIT_RESET_LSB 11 | 7 #define RESET_CONTROL_CPU_INIT_RESET_LSB 11 |
| 27 #define RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800 | 8 #define RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800 |
| 28 #define RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & RESET_CONTROL_CPU_INIT_
RESET_MASK) >> RESET_CONTROL_CPU_INIT_RESET_LSB) | 9 #define RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & RESET_CONTROL_CPU_INIT_
RESET_MASK) >> RESET_CONTROL_CPU_INIT_RESET_LSB) |
| 29 #define RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << RESET_CONTROL_CPU_INIT
_RESET_LSB) & RESET_CONTROL_CPU_INIT_RESET_MASK) | 10 #define RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << RESET_CONTROL_CPU_INIT
_RESET_LSB) & RESET_CONTROL_CPU_INIT_RESET_MASK) |
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| 1173 volatile unsigned int cpu_setup_circuit[8]; | 1154 volatile unsigned int cpu_setup_circuit[8]; |
| 1174 volatile unsigned int bb_setup_config; | 1155 volatile unsigned int bb_setup_config; |
| 1175 unsigned char pad2[28]; /* pad to 0x1a0 */ | 1156 unsigned char pad2[28]; /* pad to 0x1a0 */ |
| 1176 volatile unsigned int bb_setup_circuit[8]; | 1157 volatile unsigned int bb_setup_circuit[8]; |
| 1177 volatile unsigned int gpio_wakeup_control; | 1158 volatile unsigned int gpio_wakeup_control; |
| 1178 } rtc_reg_reg_t; | 1159 } rtc_reg_reg_t; |
| 1179 | 1160 |
| 1180 #endif /* __ASSEMBLER__ */ | 1161 #endif /* __ASSEMBLER__ */ |
| 1181 | 1162 |
| 1182 #endif /* _RTC_REG_H_ */ | 1163 #endif /* _RTC_REG_H_ */ |
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