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Side by Side Diff: chromeos/drivers/ath6kl/include/AR6002/hw/analog_intf_reg.h

Issue 3579004: ath6kl: Bringing in the upstream version (Closed) Base URL: http://git.chromium.org/git/kernel.git
Patch Set: Created 10 years, 2 months ago
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1 // ------------------------------------------------------------------
2 // Copyright (c) 2004-2007 Atheros Corporation. All rights reserved.
3 //
4 // This program is free software; you can redistribute it and/or modify
5 // it under the terms of the GNU General Public License version 2 as
6 // published by the Free Software Foundation;
7 //
8 // Software distributed under the License is distributed on an "AS
9 // IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
10 // implied. See the License for the specific language governing
11 // rights and limitations under the License.
12 //
13 //
14 // ------------------------------------------------------------------
15 //===================================================================
16 // Author(s): ="Atheros"
17 //===================================================================
18
19
20 #ifndef _ANALOG_INTF_REG_REG_H_
21 #define _ANALOG_INTF_REG_REG_H_
22
23 #define SW_OVERRIDE_ADDRESS 0x00000080
24 #define SW_OVERRIDE_OFFSET 0x00000080
25 #define SW_OVERRIDE_SUPDATE_DELAY_MSB 1
26 #define SW_OVERRIDE_SUPDATE_DELAY_LSB 1
27 #define SW_OVERRIDE_SUPDATE_DELAY_MASK 0x00000002
28 #define SW_OVERRIDE_SUPDATE_DELAY_GET(x) (((x) & SW_OVERRIDE_SUPDATE_DEL AY_MASK) >> SW_OVERRIDE_SUPDATE_DELAY_LSB)
29 #define SW_OVERRIDE_SUPDATE_DELAY_SET(x) (((x) << SW_OVERRIDE_SUPDATE_DE LAY_LSB) & SW_OVERRIDE_SUPDATE_DELAY_MASK)
30 #define SW_OVERRIDE_ENABLE_MSB 0
31 #define SW_OVERRIDE_ENABLE_LSB 0
32 #define SW_OVERRIDE_ENABLE_MASK 0x00000001
33 #define SW_OVERRIDE_ENABLE_GET(x) (((x) & SW_OVERRIDE_ENABLE_MASK ) >> SW_OVERRIDE_ENABLE_LSB)
34 #define SW_OVERRIDE_ENABLE_SET(x) (((x) << SW_OVERRIDE_ENABLE_LSB ) & SW_OVERRIDE_ENABLE_MASK)
35
36 #define SIN_VAL_ADDRESS 0x00000084
37 #define SIN_VAL_OFFSET 0x00000084
38 #define SIN_VAL_SIN_MSB 0
39 #define SIN_VAL_SIN_LSB 0
40 #define SIN_VAL_SIN_MASK 0x00000001
41 #define SIN_VAL_SIN_GET(x) (((x) & SIN_VAL_SIN_MASK) >> SI N_VAL_SIN_LSB)
42 #define SIN_VAL_SIN_SET(x) (((x) << SIN_VAL_SIN_LSB) & SIN _VAL_SIN_MASK)
43
44 #define SW_SCLK_ADDRESS 0x00000088
45 #define SW_SCLK_OFFSET 0x00000088
46 #define SW_SCLK_SW_SCLK_MSB 0
47 #define SW_SCLK_SW_SCLK_LSB 0
48 #define SW_SCLK_SW_SCLK_MASK 0x00000001
49 #define SW_SCLK_SW_SCLK_GET(x) (((x) & SW_SCLK_SW_SCLK_MASK) > > SW_SCLK_SW_SCLK_LSB)
50 #define SW_SCLK_SW_SCLK_SET(x) (((x) << SW_SCLK_SW_SCLK_LSB) & SW_SCLK_SW_SCLK_MASK)
51
52 #define SW_CNTL_ADDRESS 0x0000008c
53 #define SW_CNTL_OFFSET 0x0000008c
54 #define SW_CNTL_SW_SCAPTURE_MSB 2
55 #define SW_CNTL_SW_SCAPTURE_LSB 2
56 #define SW_CNTL_SW_SCAPTURE_MASK 0x00000004
57 #define SW_CNTL_SW_SCAPTURE_GET(x) (((x) & SW_CNTL_SW_SCAPTURE_MAS K) >> SW_CNTL_SW_SCAPTURE_LSB)
58 #define SW_CNTL_SW_SCAPTURE_SET(x) (((x) << SW_CNTL_SW_SCAPTURE_LS B) & SW_CNTL_SW_SCAPTURE_MASK)
59 #define SW_CNTL_SW_SUPDATE_MSB 1
60 #define SW_CNTL_SW_SUPDATE_LSB 1
61 #define SW_CNTL_SW_SUPDATE_MASK 0x00000002
62 #define SW_CNTL_SW_SUPDATE_GET(x) (((x) & SW_CNTL_SW_SUPDATE_MASK ) >> SW_CNTL_SW_SUPDATE_LSB)
63 #define SW_CNTL_SW_SUPDATE_SET(x) (((x) << SW_CNTL_SW_SUPDATE_LSB ) & SW_CNTL_SW_SUPDATE_MASK)
64 #define SW_CNTL_SW_SOUT_MSB 0
65 #define SW_CNTL_SW_SOUT_LSB 0
66 #define SW_CNTL_SW_SOUT_MASK 0x00000001
67 #define SW_CNTL_SW_SOUT_GET(x) (((x) & SW_CNTL_SW_SOUT_MASK) > > SW_CNTL_SW_SOUT_LSB)
68 #define SW_CNTL_SW_SOUT_SET(x) (((x) << SW_CNTL_SW_SOUT_LSB) & SW_CNTL_SW_SOUT_MASK)
69
70
71 #ifndef __ASSEMBLER__
72
73 typedef struct analog_intf_reg_reg_s {
74 unsigned char pad0[128]; /* pad to 0x80 */
75 volatile unsigned int sw_override;
76 volatile unsigned int sin_val;
77 volatile unsigned int sw_sclk;
78 volatile unsigned int sw_cntl;
79 } analog_intf_reg_reg_t;
80
81 #endif /* __ASSEMBLER__ */
82
83 #endif /* _ANALOG_INTF_REG_H_ */
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