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Side by Side Diff: chromeos/drivers/ath6kl/htc2/AR6000/ar6k.h

Issue 3579004: ath6kl: Bringing in the upstream version (Closed) Base URL: http://git.chromium.org/git/kernel.git
Patch Set: Created 10 years, 2 months ago
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1 //------------------------------------------------------------------------------ 1 //------------------------------------------------------------------------------
2 // <copyright file="ar6k.h" company="Atheros"> 2 // <copyright file="ar6k.h" company="Atheros">
3 // Copyright (c) 2007-2008 Atheros Corporation. All rights reserved. 3 // Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
4 // 4 //
5 // This program is free software; you can redistribute it and/or modify
6 // it under the terms of the GNU General Public License version 2 as
7 // published by the Free Software Foundation;
8 // 5 //
9 // Software distributed under the License is distributed on an "AS 6 // Permission to use, copy, modify, and/or distribute this software for any
10 // IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or 7 // purpose with or without fee is hereby granted, provided that the above
11 // implied. See the License for the specific language governing 8 // copyright notice and this permission notice appear in all copies.
12 // rights and limitations under the License. 9 //
10 // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
13 // 17 //
14 // 18 //
15 //------------------------------------------------------------------------------ 19 //------------------------------------------------------------------------------
16 //============================================================================== 20 //==============================================================================
17 // AR6K device layer that handles register level I/O 21 // AR6K device layer that handles register level I/O
18 // 22 //
19 // Author(s): ="Atheros" 23 // Author(s): ="Atheros"
20 //============================================================================== 24 //==============================================================================
21 #ifndef AR6K_H_ 25 #ifndef AR6K_H_
22 #define AR6K_H_ 26 #define AR6K_H_
(...skipping 51 matching lines...) Expand 10 before | Expand all | Expand 10 after
74 #define FROM_DMA_BUFFER TRUE 78 #define FROM_DMA_BUFFER TRUE
75 #define TO_DMA_BUFFER FALSE 79 #define TO_DMA_BUFFER FALSE
76 #define AR6K_SCATTER_ENTRIES_PER_REQ 16 80 #define AR6K_SCATTER_ENTRIES_PER_REQ 16
77 #define AR6K_MAX_TRANSFER_SIZE_PER_SCATTER 16*1024 81 #define AR6K_MAX_TRANSFER_SIZE_PER_SCATTER 16*1024
78 #define AR6K_SCATTER_REQS 4 82 #define AR6K_SCATTER_REQS 4
79 #define AR6K_LEGACY_MAX_WRITE_LENGTH 2048 83 #define AR6K_LEGACY_MAX_WRITE_LENGTH 2048
80 84
81 #ifndef A_CACHE_LINE_PAD 85 #ifndef A_CACHE_LINE_PAD
82 #define A_CACHE_LINE_PAD 128 86 #define A_CACHE_LINE_PAD 128
83 #endif 87 #endif
88 #define AR6K_MIN_SCATTER_ENTRIES_PER_REQ 2
89 #define AR6K_MIN_TRANSFER_SIZE_PER_SCATTER 4*1024
84 90
85 /* buffers for ASYNC I/O */ 91 /* buffers for ASYNC I/O */
86 typedef struct AR6K_ASYNC_REG_IO_BUFFER { 92 typedef struct AR6K_ASYNC_REG_IO_BUFFER {
87 HTC_PACKET HtcPacket; /* we use an HTC packet as a wrapper for our asyn c register-based I/O */ 93 HTC_PACKET HtcPacket; /* we use an HTC packet as a wrapper for our asyn c register-based I/O */
88 A_UINT8 _Pad1[A_CACHE_LINE_PAD]; 94 A_UINT8 _Pad1[A_CACHE_LINE_PAD];
89 A_UINT8 Buffer[AR6K_REG_IO_BUFFER_SIZE]; /* cache-line safe with pads around */ 95 A_UINT8 Buffer[AR6K_REG_IO_BUFFER_SIZE]; /* cache-line safe with pads around */
90 A_UINT8 _Pad2[A_CACHE_LINE_PAD]; 96 A_UINT8 _Pad2[A_CACHE_LINE_PAD];
91 } AR6K_ASYNC_REG_IO_BUFFER; 97 } AR6K_ASYNC_REG_IO_BUFFER;
92 98
93 typedef struct _AR6K_GMBOX_INFO { 99 typedef struct _AR6K_GMBOX_INFO {
(...skipping 63 matching lines...) Expand 10 before | Expand all | Expand 10 after
157 AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs); 163 AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs);
158 164
159 #define DEV_STOP_RECV_ASYNC TRUE 165 #define DEV_STOP_RECV_ASYNC TRUE
160 #define DEV_STOP_RECV_SYNC FALSE 166 #define DEV_STOP_RECV_SYNC FALSE
161 #define DEV_ENABLE_RECV_ASYNC TRUE 167 #define DEV_ENABLE_RECV_ASYNC TRUE
162 #define DEV_ENABLE_RECV_SYNC FALSE 168 #define DEV_ENABLE_RECV_SYNC FALSE
163 A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode); 169 A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
164 A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode); 170 A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
165 A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev); 171 A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev);
166 A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev); 172 A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev);
167 173 A_STATUS DevWaitForPendingRecv(AR6K_DEVICE *pDev,A_UINT32 TimeoutInMs,A_BOOL *pb IsRecvPending);
168 174
169 #define DEV_CALC_RECV_PADDED_LEN(pDev, length) (((length) + (pDev)->BlockMask) & (~((pDev)->BlockMask))) 175 #define DEV_CALC_RECV_PADDED_LEN(pDev, length) (((length) + (pDev)->BlockMask) & (~((pDev)->BlockMask)))
170 #define DEV_CALC_SEND_PADDED_LEN(pDev, length) DEV_CALC_RECV_PADDED_LEN(pDev,len gth) 176 #define DEV_CALC_SEND_PADDED_LEN(pDev, length) DEV_CALC_RECV_PADDED_LEN(pDev,len gth)
171 #define DEV_IS_LEN_BLOCK_ALIGNED(pDev, length) (((length) % (pDev)->BlockSize) = = 0) 177 #define DEV_IS_LEN_BLOCK_ALIGNED(pDev, length) (((length) % (pDev)->BlockSize) = = 0)
172 178
173 static INLINE A_STATUS DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_U INT32 SendLength) { 179 static INLINE A_STATUS DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_U INT32 SendLength) {
174 A_UINT32 paddedLength; 180 A_UINT32 paddedLength;
175 A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE; 181 A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
176 A_STATUS status; 182 A_STATUS status;
177 183
(...skipping 49 matching lines...) Expand 10 before | Expand all | Expand 10 after
227 ("DevRecvPacket, Not enough space for padlen:%d recvlen:%d buffe rlen:%d \n", 233 ("DevRecvPacket, Not enough space for padlen:%d recvlen:%d buffe rlen:%d \n",
228 paddedLength,RecvLength,pPacket->BufferLength)); 234 paddedLength,RecvLength,pPacket->BufferLength));
229 if (pPacket->Completion != NULL) { 235 if (pPacket->Completion != NULL) {
230 COMPLETE_HTC_PACKET(pPacket,A_EINVAL); 236 COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
231 return A_OK; 237 return A_OK;
232 } 238 }
233 return A_EINVAL; 239 return A_EINVAL;
234 } 240 }
235 241
236 AR_DEBUG_PRINTF(ATH_DEBUG_RECV, 242 AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
237 ("DevRecvPacket (0x%X : hdr:0x%X) Padded Length: %d Mbox:0x%X (m ode:%s)\n", 243 ("DevRecvPacket (0x%lX : hdr:0x%X) Padded Length: %d Mbox:0x%X ( mode:%s)\n",
238 (A_UINT32)pPacket, pPacket->PktInfo.AsRx.ExpectedHdr, 244 (unsigned long)pPacket, pPacket->PktInfo.AsRx.ExpectedHdr,
239 paddedLength, 245 paddedLength,
240 pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX], 246 pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
241 sync ? "SYNC" : "ASYNC")); 247 sync ? "SYNC" : "ASYNC"));
242 248
243 status = HIFReadWrite(pDev->HIFDevice, 249 status = HIFReadWrite(pDev->HIFDevice,
244 pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX], 250 pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
245 pPacket->pBuffer, 251 pPacket->pBuffer,
246 paddedLength, 252 paddedLength,
247 sync ? HIF_RD_SYNC_BLOCK_FIX : HIF_RD_ASYNC_BLOCK_FIX, 253 sync ? HIF_RD_SYNC_BLOCK_FIX : HIF_RD_ASYNC_BLOCK_FIX,
248 sync ? NULL : pPacket); /* pass the packet as the con text to the HIF request */ 254 sync ? NULL : pPacket); /* pass the packet as the con text to the HIF request */
(...skipping 134 matching lines...) Expand 10 before | Expand all | Expand 10 after
383 389
384 A_STATUS DevGMboxIRQAction(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE, A_BOOL Asyn cMode); 390 A_STATUS DevGMboxIRQAction(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE, A_BOOL Asyn cMode);
385 A_STATUS DevGMboxReadCreditCounter(AR6K_DEVICE *pDev, A_BOOL AsyncMode, int *pCr edits); 391 A_STATUS DevGMboxReadCreditCounter(AR6K_DEVICE *pDev, A_BOOL AsyncMode, int *pCr edits);
386 A_STATUS DevGMboxReadCreditSize(AR6K_DEVICE *pDev, int *pCreditSize); 392 A_STATUS DevGMboxReadCreditSize(AR6K_DEVICE *pDev, int *pCreditSize);
387 A_STATUS DevGMboxRecvLookAheadPeek(AR6K_DEVICE *pDev, A_UINT8 *pLookAheadBuffer, int *pLookAheadBytes); 393 A_STATUS DevGMboxRecvLookAheadPeek(AR6K_DEVICE *pDev, A_UINT8 *pLookAheadBuffer, int *pLookAheadBytes);
388 A_STATUS DevGMboxSetTargetInterrupt(AR6K_DEVICE *pDev, int SignalNumber, int Ack TimeoutMS); 394 A_STATUS DevGMboxSetTargetInterrupt(AR6K_DEVICE *pDev, int SignalNumber, int Ack TimeoutMS);
389 395
390 #endif 396 #endif
391 397
392 #endif /*AR6K_H_*/ 398 #endif /*AR6K_H_*/
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