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1 // Copyright 2009 the V8 project authors. All rights reserved. | 1 // Copyright 2009 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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75 | 75 |
76 #include "constants-arm.h" | 76 #include "constants-arm.h" |
77 | 77 |
78 | 78 |
79 namespace assembler { | 79 namespace assembler { |
80 namespace arm { | 80 namespace arm { |
81 | 81 |
82 class Simulator { | 82 class Simulator { |
83 public: | 83 public: |
84 friend class Debugger; | 84 friend class Debugger; |
85 | |
86 enum Register { | 85 enum Register { |
87 no_reg = -1, | 86 no_reg = -1, |
88 r0 = 0, r1, r2, r3, r4, r5, r6, r7, | 87 r0 = 0, r1, r2, r3, r4, r5, r6, r7, |
89 r8, r9, r10, r11, r12, r13, r14, r15, | 88 r8, r9, r10, r11, r12, r13, r14, r15, |
90 num_registers, | 89 num_registers, |
91 sp = 13, | 90 sp = 13, |
92 lr = 14, | 91 lr = 14, |
93 pc = 15 | 92 pc = 15, |
| 93 s0 = 0, s1, s2, s3, s4, s5, s6, s7, |
| 94 s8, s9, s10, s11, s12, s13, s14, s15, |
| 95 s16, s17, s18, s19, s20, s21, s22, s23, |
| 96 s24, s25, s26, s27, s28, s29, s30, s31, |
| 97 num_s_registers = 32, |
| 98 d0 = 0, d1, d2, d3, d4, d5, d6, d7, |
| 99 d8, d9, d10, d11, d12, d13, d14, d15, |
| 100 num_d_registers = 16 |
94 }; | 101 }; |
95 | 102 |
96 Simulator(); | 103 Simulator(); |
97 ~Simulator(); | 104 ~Simulator(); |
98 | 105 |
99 // The currently executing Simulator instance. Potentially there can be one | 106 // The currently executing Simulator instance. Potentially there can be one |
100 // for each native thread. | 107 // for each native thread. |
101 static Simulator* current(); | 108 static Simulator* current(); |
102 | 109 |
103 // Accessors for register state. Reading the pc value adheres to the ARM | 110 // Accessors for register state. Reading the pc value adheres to the ARM |
104 // architecture specification and is off by a 8 from the currently executing | 111 // architecture specification and is off by a 8 from the currently executing |
105 // instruction. | 112 // instruction. |
106 void set_register(int reg, int32_t value); | 113 void set_register(int reg, int32_t value); |
107 int32_t get_register(int reg) const; | 114 int32_t get_register(int reg) const; |
108 | 115 |
| 116 // Support for VFP. |
| 117 void set_s_register(int reg, unsigned int value); |
| 118 unsigned int get_s_register(int reg) const; |
| 119 void set_d_register_from_double(int dreg, const double& dbl); |
| 120 double get_double_from_d_register(int dreg); |
| 121 void set_s_register_from_float(int sreg, const float dbl); |
| 122 float get_float_from_s_register(int sreg); |
| 123 void set_s_register_from_sinteger(int reg, const int value); |
| 124 int get_sinteger_from_s_register(int reg); |
| 125 |
109 // Special case of set_register and get_register to access the raw PC value. | 126 // Special case of set_register and get_register to access the raw PC value. |
110 void set_pc(int32_t value); | 127 void set_pc(int32_t value); |
111 int32_t get_pc() const; | 128 int32_t get_pc() const; |
112 | 129 |
113 // Accessor to the internal simulator stack area. | 130 // Accessor to the internal simulator stack area. |
114 uintptr_t StackLimit() const; | 131 uintptr_t StackLimit() const; |
115 | 132 |
116 // Executes ARM instructions until the PC reaches end_sim_pc. | 133 // Executes ARM instructions until the PC reaches end_sim_pc. |
117 void Execute(); | 134 void Execute(); |
118 | 135 |
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147 void SetNZFlags(int32_t val); | 164 void SetNZFlags(int32_t val); |
148 void SetCFlag(bool val); | 165 void SetCFlag(bool val); |
149 void SetVFlag(bool val); | 166 void SetVFlag(bool val); |
150 bool CarryFrom(int32_t left, int32_t right); | 167 bool CarryFrom(int32_t left, int32_t right); |
151 bool BorrowFrom(int32_t left, int32_t right); | 168 bool BorrowFrom(int32_t left, int32_t right); |
152 bool OverflowFrom(int32_t alu_out, | 169 bool OverflowFrom(int32_t alu_out, |
153 int32_t left, | 170 int32_t left, |
154 int32_t right, | 171 int32_t right, |
155 bool addition); | 172 bool addition); |
156 | 173 |
| 174 // Support for VFP. |
| 175 void Compute_FPSCR_Flags(double val1, double val2); |
| 176 void Copy_FPSCR_to_APSR(); |
| 177 |
157 // Helper functions to decode common "addressing" modes | 178 // Helper functions to decode common "addressing" modes |
158 int32_t GetShiftRm(Instr* instr, bool* carry_out); | 179 int32_t GetShiftRm(Instr* instr, bool* carry_out); |
159 int32_t GetImm(Instr* instr, bool* carry_out); | 180 int32_t GetImm(Instr* instr, bool* carry_out); |
160 void HandleRList(Instr* instr, bool load); | 181 void HandleRList(Instr* instr, bool load); |
161 void SoftwareInterrupt(Instr* instr); | 182 void SoftwareInterrupt(Instr* instr); |
162 | 183 |
163 // Read and write memory. | 184 // Read and write memory. |
164 inline uint8_t ReadBU(int32_t addr); | 185 inline uint8_t ReadBU(int32_t addr); |
165 inline int8_t ReadB(int32_t addr); | 186 inline int8_t ReadB(int32_t addr); |
166 inline void WriteB(int32_t addr, uint8_t value); | 187 inline void WriteB(int32_t addr, uint8_t value); |
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178 // Executing is handled based on the instruction type. | 199 // Executing is handled based on the instruction type. |
179 void DecodeType01(Instr* instr); // both type 0 and type 1 rolled into one | 200 void DecodeType01(Instr* instr); // both type 0 and type 1 rolled into one |
180 void DecodeType2(Instr* instr); | 201 void DecodeType2(Instr* instr); |
181 void DecodeType3(Instr* instr); | 202 void DecodeType3(Instr* instr); |
182 void DecodeType4(Instr* instr); | 203 void DecodeType4(Instr* instr); |
183 void DecodeType5(Instr* instr); | 204 void DecodeType5(Instr* instr); |
184 void DecodeType6(Instr* instr); | 205 void DecodeType6(Instr* instr); |
185 void DecodeType7(Instr* instr); | 206 void DecodeType7(Instr* instr); |
186 void DecodeUnconditional(Instr* instr); | 207 void DecodeUnconditional(Instr* instr); |
187 | 208 |
| 209 // Support for VFP. |
| 210 void DecodeTypeVFP(Instr* instr); |
| 211 void DecodeType6CoprocessorIns(Instr* instr); |
| 212 |
188 // Executes one instruction. | 213 // Executes one instruction. |
189 void InstructionDecode(Instr* instr); | 214 void InstructionDecode(Instr* instr); |
190 | 215 |
191 // Runtime call support. | 216 // Runtime call support. |
192 static void* RedirectExternalReference(void* external_function, | 217 static void* RedirectExternalReference(void* external_function, |
193 bool fp_return); | 218 bool fp_return); |
194 | 219 |
195 // For use in calls that take two double values, constructed from r0, r1, r2 | 220 // For use in calls that take two double values, constructed from r0, r1, r2 |
196 // and r3. | 221 // and r3. |
197 void GetFpArgs(double* x, double* y); | 222 void GetFpArgs(double* x, double* y); |
198 void SetFpResult(const double& result); | 223 void SetFpResult(const double& result); |
199 void TrashCallerSaveRegisters(); | 224 void TrashCallerSaveRegisters(); |
200 | 225 |
201 // architecture state | 226 // architecture state |
202 int32_t registers_[16]; | 227 int32_t registers_[16]; |
203 bool n_flag_; | 228 bool n_flag_; |
204 bool z_flag_; | 229 bool z_flag_; |
205 bool c_flag_; | 230 bool c_flag_; |
206 bool v_flag_; | 231 bool v_flag_; |
207 | 232 |
| 233 // VFP architecture state. |
| 234 unsigned int vfp_register[32/*num_s_registers*/]; |
| 235 bool n_flag_FPSCR_; |
| 236 bool z_flag_FPSCR_; |
| 237 bool c_flag_FPSCR_; |
| 238 bool v_flag_FPSCR_; |
| 239 |
| 240 // VFP FP exception flags architecture state. |
| 241 bool inv_op_vfp_flag_; |
| 242 bool div_zero_vfp_flag_; |
| 243 bool overflow_vfp_flag_; |
| 244 bool underflow_vfp_flag_; |
| 245 bool inexact_vfp_flag_; |
| 246 |
208 // simulator support | 247 // simulator support |
209 char* stack_; | 248 char* stack_; |
210 bool pc_modified_; | 249 bool pc_modified_; |
211 int icount_; | 250 int icount_; |
212 static bool initialized_; | 251 static bool initialized_; |
213 | 252 |
214 // registered breakpoints | 253 // registered breakpoints |
215 Instr* break_pc_; | 254 Instr* break_pc_; |
216 instr_t break_instr_; | 255 instr_t break_instr_; |
217 }; | 256 }; |
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228 public: | 267 public: |
229 static inline uintptr_t JsLimitFromCLimit(uintptr_t c_limit) { | 268 static inline uintptr_t JsLimitFromCLimit(uintptr_t c_limit) { |
230 return assembler::arm::Simulator::current()->StackLimit(); | 269 return assembler::arm::Simulator::current()->StackLimit(); |
231 } | 270 } |
232 }; | 271 }; |
233 | 272 |
234 | 273 |
235 #endif // defined(__arm__) | 274 #endif // defined(__arm__) |
236 | 275 |
237 #endif // V8_ARM_SIMULATOR_ARM_H_ | 276 #endif // V8_ARM_SIMULATOR_ARM_H_ |
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