Add vfp support on ARM. Patch from John Jozwiak.

src/arm/constants-arm.h

 // Copyright 2009 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 57 matching lines @@
 # define CAN_USE_ARMV5_INSTRUCTIONS 1
 # define CAN_USE_THUMB_INSTRUCTIONS 1
 #endif
 
 namespace assembler {
 namespace arm {
 
 // Number of registers in normal ARM mode.
 static const int kNumRegisters = 16;
 
+// VFP support.
+static const int kNumVFPRegisters = 48;
+
 // PC is register 15.
 static const int kPCRegister = 15;
 static const int kNoRegister = -1;
 
 // Defines constants and accessor classes to assemble, disassemble and
 // simulate ARM instructions.
 //
 // Section references in the code refer to the "ARM Architecture Reference
 // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf)
 //
@@ skipping 136 matching lines @@
   // The naming of these accessor corresponds to figure A3-1.
   // Generally applicable fields
   inline Condition ConditionField() const {
     return static_cast<Condition>(Bits(31, 28));
   }
   inline int TypeField() const { return Bits(27, 25); }
 
   inline int RnField() const { return Bits(19, 16); }
   inline int RdField() const { return Bits(15, 12); }
 
+  // Support for VFP.
+  // Vn(19-16) | Vd(15-12) |  Vm(3-0)
+  inline int VnField() const { return Bits(19, 16); }
+  inline int VmField() const { return Bits(3, 0); }
+  inline int VdField() const { return Bits(15, 12); }
+  inline int NField() const { return Bit(7); }
+  inline int MField() const { return Bit(5); }
+  inline int DField() const { return Bit(22); }
+  inline int RtField() const { return Bits(15, 12); }
+
   // Fields used in Data processing instructions
   inline Opcode OpcodeField() const {
     return static_cast<Opcode>(Bits(24, 21));
   }
   inline int SField() const { return Bit(20); }
     // with register
   inline int RmField() const { return Bits(3, 0); }
   inline Shift ShiftField() const { return static_cast<Shift>(Bits(6, 5)); }
   inline int RegShiftField() const { return Bit(4); }
   inline int RsField() const { return Bits(11, 8); }
@@ skipping 64 matching lines @@
   struct RegisterAlias {
     int reg;
     const char *name;
   };
 
  private:
   static const char* names_[kNumRegisters];
   static const RegisterAlias aliases_[];
 };
 
+// Helper functions for converting between VFP register numbers and names.
+class VFPRegisters {
+ public:
+  // Return the name of the register.
+  static const char* Name(int reg);
+
+ private:
+  static const char* names_[kNumVFPRegisters];
+};
 
 
 } }  // namespace assembler::arm
 
 #endif  // V8_ARM_CONSTANTS_ARM_H_