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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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95 extern Register r7; | 95 extern Register r7; |
96 extern Register r8; | 96 extern Register r8; |
97 extern Register r9; | 97 extern Register r9; |
98 extern Register r10; | 98 extern Register r10; |
99 extern Register fp; | 99 extern Register fp; |
100 extern Register ip; | 100 extern Register ip; |
101 extern Register sp; | 101 extern Register sp; |
102 extern Register lr; | 102 extern Register lr; |
103 extern Register pc; | 103 extern Register pc; |
104 | 104 |
| 105 // Support for VFP registers s0 to s32 (d0 to d16). |
| 106 // Note that "sN:sM" is the same as "dN/2". |
| 107 extern Register s0; |
| 108 extern Register s1; |
| 109 extern Register s2; |
| 110 extern Register s3; |
| 111 extern Register s4; |
| 112 extern Register s5; |
| 113 extern Register s6; |
| 114 extern Register s7; |
| 115 extern Register s8; |
| 116 extern Register s9; |
| 117 extern Register s10; |
| 118 extern Register s11; |
| 119 extern Register s12; |
| 120 extern Register s13; |
| 121 extern Register s14; |
| 122 extern Register s15; |
| 123 extern Register s16; |
| 124 extern Register s17; |
| 125 extern Register s18; |
| 126 extern Register s19; |
| 127 extern Register s20; |
| 128 extern Register s21; |
| 129 extern Register s22; |
| 130 extern Register s23; |
| 131 extern Register s24; |
| 132 extern Register s25; |
| 133 extern Register s26; |
| 134 extern Register s27; |
| 135 extern Register s28; |
| 136 extern Register s29; |
| 137 extern Register s30; |
| 138 extern Register s31; |
| 139 |
| 140 extern Register d0; |
| 141 extern Register d1; |
| 142 extern Register d2; |
| 143 extern Register d3; |
| 144 extern Register d4; |
| 145 extern Register d5; |
| 146 extern Register d6; |
| 147 extern Register d7; |
| 148 extern Register d8; |
| 149 extern Register d9; |
| 150 extern Register d10; |
| 151 extern Register d11; |
| 152 extern Register d12; |
| 153 extern Register d13; |
| 154 extern Register d14; |
| 155 extern Register d15; |
105 | 156 |
106 // Coprocessor register | 157 // Coprocessor register |
107 struct CRegister { | 158 struct CRegister { |
108 bool is_valid() const { return 0 <= code_ && code_ < 16; } | 159 bool is_valid() const { return 0 <= code_ && code_ < 16; } |
109 bool is(CRegister creg) const { return code_ == creg.code_; } | 160 bool is(CRegister creg) const { return code_ == creg.code_; } |
110 int code() const { | 161 int code() const { |
111 ASSERT(is_valid()); | 162 ASSERT(is_valid()); |
112 return code_; | 163 return code_; |
113 } | 164 } |
114 int bit() const { | 165 int bit() const { |
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365 Register rn_; // base | 416 Register rn_; // base |
366 Register rm_; // register offset | 417 Register rm_; // register offset |
367 int32_t offset_; // valid if rm_ == no_reg | 418 int32_t offset_; // valid if rm_ == no_reg |
368 ShiftOp shift_op_; | 419 ShiftOp shift_op_; |
369 int shift_imm_; // valid if rm_ != no_reg && rs_ == no_reg | 420 int shift_imm_; // valid if rm_ != no_reg && rs_ == no_reg |
370 AddrMode am_; // bits P, U, and W | 421 AddrMode am_; // bits P, U, and W |
371 | 422 |
372 friend class Assembler; | 423 friend class Assembler; |
373 }; | 424 }; |
374 | 425 |
| 426 // CpuFeatures keeps track of which features are supported by the target CPU. |
| 427 // Supported features must be enabled by a Scope before use. |
| 428 class CpuFeatures : public AllStatic { |
| 429 public: |
| 430 enum Feature { VFP3 = 1 }; |
| 431 // Detect features of the target CPU. Set safe defaults if the serializer |
| 432 // is enabled (snapshots must be portable). |
| 433 static void Probe(); |
| 434 // Check whether a feature is supported by the target CPU. |
| 435 static bool IsSupported(Feature f) { |
| 436 if (f == VFP3 && !FLAG_enable_vfp3) return false; |
| 437 |
| 438 return (supported_ & (static_cast<uint64_t>(1) << f)) != 0; |
| 439 } |
| 440 // Check whether a feature is currently enabled. |
| 441 static bool IsEnabled(Feature f) { |
| 442 return (enabled_ & (static_cast<uint64_t>(1) << f)) != 0; |
| 443 } |
| 444 |
| 445 private: |
| 446 static uint64_t supported_; |
| 447 static uint64_t enabled_; |
| 448 }; |
| 449 |
375 | 450 |
376 typedef int32_t Instr; | 451 typedef int32_t Instr; |
377 | 452 |
378 | 453 |
379 extern const Instr kMovLrPc; | 454 extern const Instr kMovLrPc; |
380 extern const Instr kLdrPCPattern; | 455 extern const Instr kLdrPCPattern; |
381 | 456 |
382 | 457 |
383 class Assembler : public Malloced { | 458 class Assembler : public Malloced { |
384 public: | 459 public: |
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648 void stc(Coprocessor coproc, CRegister crd, const MemOperand& dst, | 723 void stc(Coprocessor coproc, CRegister crd, const MemOperand& dst, |
649 LFlag l = Short, Condition cond = al); | 724 LFlag l = Short, Condition cond = al); |
650 void stc(Coprocessor coproc, CRegister crd, Register base, int option, | 725 void stc(Coprocessor coproc, CRegister crd, Register base, int option, |
651 LFlag l = Short, Condition cond = al); | 726 LFlag l = Short, Condition cond = al); |
652 | 727 |
653 void stc2(Coprocessor coproc, CRegister crd, const MemOperand& dst, | 728 void stc2(Coprocessor coproc, CRegister crd, const MemOperand& dst, |
654 LFlag l = Short); // v5 and above | 729 LFlag l = Short); // v5 and above |
655 void stc2(Coprocessor coproc, CRegister crd, Register base, int option, | 730 void stc2(Coprocessor coproc, CRegister crd, Register base, int option, |
656 LFlag l = Short); // v5 and above | 731 LFlag l = Short); // v5 and above |
657 | 732 |
| 733 // Support for VFP. |
| 734 // All these APIs support S0 to S31 and D0 to D15. |
| 735 // Currently these APIs do not support extended D registers, i.e, D16 to D31. |
| 736 // However, some simple modifications can allow |
| 737 // these APIs to support D16 to D31. |
| 738 |
| 739 void fmdrr(const Register dst, |
| 740 const Register src1, |
| 741 const Register src2, |
| 742 const SBit s = LeaveCC, |
| 743 const Condition cond = al); |
| 744 void fmrrd(const Register dst1, |
| 745 const Register dst2, |
| 746 const Register src, |
| 747 const SBit s = LeaveCC, |
| 748 const Condition cond = al); |
| 749 void fmsr(const Register dst, |
| 750 const Register src, |
| 751 const SBit s = LeaveCC, |
| 752 const Condition cond = al); |
| 753 void fmrs(const Register dst, |
| 754 const Register src, |
| 755 const SBit s = LeaveCC, |
| 756 const Condition cond = al); |
| 757 void fsitod(const Register dst, |
| 758 const Register src, |
| 759 const SBit s = LeaveCC, |
| 760 const Condition cond = al); |
| 761 void ftosid(const Register dst, |
| 762 const Register src, |
| 763 const SBit s = LeaveCC, |
| 764 const Condition cond = al); |
| 765 |
| 766 void faddd(const Register dst, |
| 767 const Register src1, |
| 768 const Register src2, |
| 769 const SBit s = LeaveCC, |
| 770 const Condition cond = al); |
| 771 void fsubd(const Register dst, |
| 772 const Register src1, |
| 773 const Register src2, |
| 774 const SBit s = LeaveCC, |
| 775 const Condition cond = al); |
| 776 void fmuld(const Register dst, |
| 777 const Register src1, |
| 778 const Register src2, |
| 779 const SBit s = LeaveCC, |
| 780 const Condition cond = al); |
| 781 void fdivd(const Register dst, |
| 782 const Register src1, |
| 783 const Register src2, |
| 784 const SBit s = LeaveCC, |
| 785 const Condition cond = al); |
| 786 void fcmp(const Register src1, |
| 787 const Register src2, |
| 788 const SBit s = LeaveCC, |
| 789 const Condition cond = al); |
| 790 void vmrs(const Register dst, |
| 791 const Condition cond = al); |
| 792 |
658 // Pseudo instructions | 793 // Pseudo instructions |
659 void nop() { mov(r0, Operand(r0)); } | 794 void nop() { mov(r0, Operand(r0)); } |
660 | 795 |
661 void push(Register src, Condition cond = al) { | 796 void push(Register src, Condition cond = al) { |
662 str(src, MemOperand(sp, 4, NegPreIndex), cond); | 797 str(src, MemOperand(sp, 4, NegPreIndex), cond); |
663 } | 798 } |
664 | 799 |
665 void pop(Register dst, Condition cond = al) { | 800 void pop(Register dst, Condition cond = al) { |
666 ldr(dst, MemOperand(sp, 4, PostIndex), cond); | 801 ldr(dst, MemOperand(sp, 4, PostIndex), cond); |
667 } | 802 } |
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826 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); | 961 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); |
827 | 962 |
828 friend class RegExpMacroAssemblerARM; | 963 friend class RegExpMacroAssemblerARM; |
829 friend class RelocInfo; | 964 friend class RelocInfo; |
830 friend class CodePatcher; | 965 friend class CodePatcher; |
831 }; | 966 }; |
832 | 967 |
833 } } // namespace v8::internal | 968 } } // namespace v8::internal |
834 | 969 |
835 #endif // V8_ARM_ASSEMBLER_ARM_H_ | 970 #endif // V8_ARM_ASSEMBLER_ARM_H_ |
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