Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(862)

Side by Side Diff: src/arm/assembler-arm.h

Issue 3427021: Fix some inconsistent formatting. (Closed)
Patch Set: Created 10 years, 3 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « no previous file | src/arm/codegen-arm.h » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
(...skipping 51 matching lines...) Expand 10 before | Expand all | Expand 10 after
62 // 3) By not using an enum, we are possibly preventing the compiler from 62 // 3) By not using an enum, we are possibly preventing the compiler from
63 // doing certain constant folds, which may significantly reduce the 63 // doing certain constant folds, which may significantly reduce the
64 // code generated for some assembly instructions (because they boil down 64 // code generated for some assembly instructions (because they boil down
65 // to a few constants). If this is a problem, we could change the code 65 // to a few constants). If this is a problem, we could change the code
66 // such that we use an enum in optimized mode, and the struct in debug 66 // such that we use an enum in optimized mode, and the struct in debug
67 // mode. This way we get the compile-time error checking in debug mode 67 // mode. This way we get the compile-time error checking in debug mode
68 // and best performance in optimized code. 68 // and best performance in optimized code.
69 // 69 //
70 // Core register 70 // Core register
71 struct Register { 71 struct Register {
72 bool is_valid() const { return 0 <= code_ && code_ < 16; } 72 bool is_valid() const { return 0 <= code_ && code_ < 16; }
73 bool is(Register reg) const { return code_ == reg.code_; } 73 bool is(Register reg) const { return code_ == reg.code_; }
74 int code() const { 74 int code() const {
75 ASSERT(is_valid()); 75 ASSERT(is_valid());
76 return code_; 76 return code_;
77 } 77 }
78 int bit() const { 78 int bit() const {
79 ASSERT(is_valid()); 79 ASSERT(is_valid());
80 return 1 << code_; 80 return 1 << code_;
81 } 81 }
82 82
83 void set_code(int code) { 83 void set_code(int code) {
84 code_ = code; 84 code_ = code;
85 ASSERT(is_valid()); 85 ASSERT(is_valid());
86 } 86 }
87 87
88 // Unfortunately we can't make this private in a struct. 88 // Unfortunately we can't make this private in a struct.
(...skipping 14 matching lines...) Expand all
103 const Register r9 = { 9 }; 103 const Register r9 = { 9 };
104 const Register r10 = { 10 }; // Used as roots register. 104 const Register r10 = { 10 }; // Used as roots register.
105 const Register fp = { 11 }; 105 const Register fp = { 11 };
106 const Register ip = { 12 }; 106 const Register ip = { 12 };
107 const Register sp = { 13 }; 107 const Register sp = { 13 };
108 const Register lr = { 14 }; 108 const Register lr = { 14 };
109 const Register pc = { 15 }; 109 const Register pc = { 15 };
110 110
111 // Single word VFP register. 111 // Single word VFP register.
112 struct SwVfpRegister { 112 struct SwVfpRegister {
113 bool is_valid() const { return 0 <= code_ && code_ < 32; } 113 bool is_valid() const { return 0 <= code_ && code_ < 32; }
114 bool is(SwVfpRegister reg) const { return code_ == reg.code_; } 114 bool is(SwVfpRegister reg) const { return code_ == reg.code_; }
115 int code() const { 115 int code() const {
116 ASSERT(is_valid()); 116 ASSERT(is_valid());
117 return code_; 117 return code_;
118 } 118 }
119 int bit() const { 119 int bit() const {
120 ASSERT(is_valid()); 120 ASSERT(is_valid());
121 return 1 << code_; 121 return 1 << code_;
122 } 122 }
123 void split_code(int* vm, int* m) const { 123 void split_code(int* vm, int* m) const {
124 ASSERT(is_valid()); 124 ASSERT(is_valid());
125 *m = code_ & 0x1; 125 *m = code_ & 0x1;
126 *vm = code_ >> 1; 126 *vm = code_ >> 1;
127 } 127 }
128 128
129 int code_; 129 int code_;
130 }; 130 };
131 131
132 132
133 // Double word VFP register. 133 // Double word VFP register.
134 struct DwVfpRegister { 134 struct DwVfpRegister {
135 // Supporting d0 to d15, can be later extended to d31. 135 // Supporting d0 to d15, can be later extended to d31.
136 bool is_valid() const { return 0 <= code_ && code_ < 16; } 136 bool is_valid() const { return 0 <= code_ && code_ < 16; }
137 bool is(DwVfpRegister reg) const { return code_ == reg.code_; } 137 bool is(DwVfpRegister reg) const { return code_ == reg.code_; }
138 SwVfpRegister low() const { 138 SwVfpRegister low() const {
139 SwVfpRegister reg; 139 SwVfpRegister reg;
140 reg.code_ = code_ * 2; 140 reg.code_ = code_ * 2;
141 141
142 ASSERT(reg.is_valid()); 142 ASSERT(reg.is_valid());
143 return reg; 143 return reg;
144 } 144 }
145 SwVfpRegister high() const { 145 SwVfpRegister high() const {
146 SwVfpRegister reg; 146 SwVfpRegister reg;
147 reg.code_ = (code_ * 2) + 1; 147 reg.code_ = (code_ * 2) + 1;
148 148
149 ASSERT(reg.is_valid()); 149 ASSERT(reg.is_valid());
150 return reg; 150 return reg;
151 } 151 }
152 int code() const { 152 int code() const {
153 ASSERT(is_valid()); 153 ASSERT(is_valid());
154 return code_; 154 return code_;
155 } 155 }
156 int bit() const { 156 int bit() const {
157 ASSERT(is_valid()); 157 ASSERT(is_valid());
158 return 1 << code_; 158 return 1 << code_;
159 } 159 }
160 void split_code(int* vm, int* m) const { 160 void split_code(int* vm, int* m) const {
161 ASSERT(is_valid()); 161 ASSERT(is_valid());
162 *m = (code_ & 0x10) >> 4; 162 *m = (code_ & 0x10) >> 4;
163 *vm = code_ & 0x0F; 163 *vm = code_ & 0x0F;
164 } 164 }
165 165
166 int code_; 166 int code_;
167 }; 167 };
168 168
169 169
170 // Support for the VFP registers s0 to s31 (d0 to d15). 170 // Support for the VFP registers s0 to s31 (d0 to d15).
(...skipping 44 matching lines...) Expand 10 before | Expand all | Expand 10 after
215 const DwVfpRegister d10 = { 10 }; 215 const DwVfpRegister d10 = { 10 };
216 const DwVfpRegister d11 = { 11 }; 216 const DwVfpRegister d11 = { 11 };
217 const DwVfpRegister d12 = { 12 }; 217 const DwVfpRegister d12 = { 12 };
218 const DwVfpRegister d13 = { 13 }; 218 const DwVfpRegister d13 = { 13 };
219 const DwVfpRegister d14 = { 14 }; 219 const DwVfpRegister d14 = { 14 };
220 const DwVfpRegister d15 = { 15 }; 220 const DwVfpRegister d15 = { 15 };
221 221
222 222
223 // Coprocessor register 223 // Coprocessor register
224 struct CRegister { 224 struct CRegister {
225 bool is_valid() const { return 0 <= code_ && code_ < 16; } 225 bool is_valid() const { return 0 <= code_ && code_ < 16; }
226 bool is(CRegister creg) const { return code_ == creg.code_; } 226 bool is(CRegister creg) const { return code_ == creg.code_; }
227 int code() const { 227 int code() const {
228 ASSERT(is_valid()); 228 ASSERT(is_valid());
229 return code_; 229 return code_;
230 } 230 }
231 int bit() const { 231 int bit() const {
232 ASSERT(is_valid()); 232 ASSERT(is_valid());
233 return 1 << code_; 233 return 1 << code_;
234 } 234 }
235 235
236 // Unfortunately we can't make this private in a struct. 236 // Unfortunately we can't make this private in a struct.
237 int code_; 237 int code_;
238 }; 238 };
239 239
240 240
241 const CRegister no_creg = { -1 }; 241 const CRegister no_creg = { -1 };
(...skipping 1043 matching lines...) Expand 10 before | Expand all | Expand 10 after
1285 1285
1286 friend class RegExpMacroAssemblerARM; 1286 friend class RegExpMacroAssemblerARM;
1287 friend class RelocInfo; 1287 friend class RelocInfo;
1288 friend class CodePatcher; 1288 friend class CodePatcher;
1289 friend class BlockConstPoolScope; 1289 friend class BlockConstPoolScope;
1290 }; 1290 };
1291 1291
1292 } } // namespace v8::internal 1292 } } // namespace v8::internal
1293 1293
1294 #endif // V8_ARM_ASSEMBLER_ARM_H_ 1294 #endif // V8_ARM_ASSEMBLER_ARM_H_
OLDNEW
« no previous file with comments | « no previous file | src/arm/codegen-arm.h » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698