| Index: src/ia32/assembler-ia32.cc
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| diff --git a/src/ia32/assembler-ia32.cc b/src/ia32/assembler-ia32.cc
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| index eef307d7ed2e45a5dc6e02172b3978e8c7f5bbce..8ea37800d36c0067f41c062426ace7597c7725ca 100644
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| --- a/src/ia32/assembler-ia32.cc
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| +++ b/src/ia32/assembler-ia32.cc
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| @@ -2179,6 +2179,16 @@ void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
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|  }
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|  
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|  
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| +void Assembler::andpd(XMMRegister dst, const Operand& src) {
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| +  EnsureSpace ensure_space(this);
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| +  last_pc_ = pc_;
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| +  EMIT(0x66);
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| +  EMIT(0x0F);
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| +  EMIT(0x54);
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| +  emit_sse_operand(dst, src);
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| +}
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| +
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| +
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|  void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
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|    ASSERT(CpuFeatures::IsEnabled(SSE2));
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|    EnsureSpace ensure_space(this);
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| @@ -2201,7 +2211,29 @@ void Assembler::movmskpd(Register dst, XMMRegister src) {
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|  }
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|  
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|  
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| -void Assembler::movdqa(const Operand& dst, XMMRegister src ) {
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| +void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) {
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| +  ASSERT(CpuFeatures::IsEnabled(SSE2));
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| +  EnsureSpace ensure_space(this);
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| +  last_pc_ = pc_;
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| +  EMIT(0xF2);
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| +  EMIT(0x0F);
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| +  EMIT(0xC2);
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| +  emit_sse_operand(dst, src);
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| +  EMIT(1);  // LT == 1
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| +}
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| +
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| +
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| +void Assembler::movaps(XMMRegister dst, const Operand& src) {
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| +  ASSERT(CpuFeatures::IsEnabled(SSE2));
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| +  EnsureSpace ensure_space(this);
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| +  last_pc_ = pc_;
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| +  EMIT(0x0F);
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| +  EMIT(0x28);
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| +  emit_sse_operand(dst, src);
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| +}
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| +
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| +
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| +void Assembler::movdqa(const Operand& dst, XMMRegister src) {
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|    ASSERT(CpuFeatures::IsEnabled(SSE2));
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|    EnsureSpace ensure_space(this);
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|    last_pc_ = pc_;
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| @@ -2358,6 +2390,19 @@ void Assembler::ptest(XMMRegister dst, XMMRegister src) {
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|    emit_sse_operand(dst, src);
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|  }
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|  
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| +
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| +void Assembler::psllq(XMMRegister reg, int8_t imm8) {
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| +  ASSERT(CpuFeatures::IsEnabled(SSE2));
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| +  EnsureSpace ensure_space(this);
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| +  last_pc_ = pc_;
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| +  EMIT(0x66);
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| +  EMIT(0x0F);
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| +  EMIT(0x73);
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| +  emit_sse_operand(esi, reg);  // esi == 6
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| +  EMIT(imm8);
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| +}
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| +
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| +
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|  void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) {
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|    Register ireg = { reg.code() };
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|    emit_operand(ireg, adr);
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| 
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