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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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2172 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { | 2172 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
2173 EnsureSpace ensure_space(this); | 2173 EnsureSpace ensure_space(this); |
2174 last_pc_ = pc_; | 2174 last_pc_ = pc_; |
2175 EMIT(0xF2); | 2175 EMIT(0xF2); |
2176 EMIT(0x0F); | 2176 EMIT(0x0F); |
2177 EMIT(0x51); | 2177 EMIT(0x51); |
2178 emit_sse_operand(dst, src); | 2178 emit_sse_operand(dst, src); |
2179 } | 2179 } |
2180 | 2180 |
2181 | 2181 |
| 2182 void Assembler::andpd(XMMRegister dst, const Operand& src) { |
| 2183 EnsureSpace ensure_space(this); |
| 2184 last_pc_ = pc_; |
| 2185 EMIT(0x66); |
| 2186 EMIT(0x0F); |
| 2187 EMIT(0x54); |
| 2188 emit_sse_operand(dst, src); |
| 2189 } |
| 2190 |
| 2191 |
2182 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | 2192 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { |
2183 ASSERT(CpuFeatures::IsEnabled(SSE2)); | 2193 ASSERT(CpuFeatures::IsEnabled(SSE2)); |
2184 EnsureSpace ensure_space(this); | 2194 EnsureSpace ensure_space(this); |
2185 last_pc_ = pc_; | 2195 last_pc_ = pc_; |
2186 EMIT(0x66); | 2196 EMIT(0x66); |
2187 EMIT(0x0F); | 2197 EMIT(0x0F); |
2188 EMIT(0x2E); | 2198 EMIT(0x2E); |
2189 emit_sse_operand(dst, src); | 2199 emit_sse_operand(dst, src); |
2190 } | 2200 } |
2191 | 2201 |
2192 | 2202 |
2193 void Assembler::movmskpd(Register dst, XMMRegister src) { | 2203 void Assembler::movmskpd(Register dst, XMMRegister src) { |
2194 ASSERT(CpuFeatures::IsEnabled(SSE2)); | 2204 ASSERT(CpuFeatures::IsEnabled(SSE2)); |
2195 EnsureSpace ensure_space(this); | 2205 EnsureSpace ensure_space(this); |
2196 last_pc_ = pc_; | 2206 last_pc_ = pc_; |
2197 EMIT(0x66); | 2207 EMIT(0x66); |
2198 EMIT(0x0F); | 2208 EMIT(0x0F); |
2199 EMIT(0x50); | 2209 EMIT(0x50); |
2200 emit_sse_operand(dst, src); | 2210 emit_sse_operand(dst, src); |
2201 } | 2211 } |
2202 | 2212 |
2203 | 2213 |
2204 void Assembler::movdqa(const Operand& dst, XMMRegister src ) { | 2214 void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) { |
2205 ASSERT(CpuFeatures::IsEnabled(SSE2)); | 2215 ASSERT(CpuFeatures::IsEnabled(SSE2)); |
2206 EnsureSpace ensure_space(this); | 2216 EnsureSpace ensure_space(this); |
2207 last_pc_ = pc_; | 2217 last_pc_ = pc_; |
| 2218 EMIT(0xF2); |
| 2219 EMIT(0x0F); |
| 2220 EMIT(0xC2); |
| 2221 emit_sse_operand(dst, src); |
| 2222 EMIT(1); // LT == 1 |
| 2223 } |
| 2224 |
| 2225 |
| 2226 void Assembler::movaps(XMMRegister dst, const Operand& src) { |
| 2227 ASSERT(CpuFeatures::IsEnabled(SSE2)); |
| 2228 EnsureSpace ensure_space(this); |
| 2229 last_pc_ = pc_; |
| 2230 EMIT(0x0F); |
| 2231 EMIT(0x28); |
| 2232 emit_sse_operand(dst, src); |
| 2233 } |
| 2234 |
| 2235 |
| 2236 void Assembler::movdqa(const Operand& dst, XMMRegister src) { |
| 2237 ASSERT(CpuFeatures::IsEnabled(SSE2)); |
| 2238 EnsureSpace ensure_space(this); |
| 2239 last_pc_ = pc_; |
2208 EMIT(0x66); | 2240 EMIT(0x66); |
2209 EMIT(0x0F); | 2241 EMIT(0x0F); |
2210 EMIT(0x7F); | 2242 EMIT(0x7F); |
2211 emit_sse_operand(src, dst); | 2243 emit_sse_operand(src, dst); |
2212 } | 2244 } |
2213 | 2245 |
2214 | 2246 |
2215 void Assembler::movdqa(XMMRegister dst, const Operand& src) { | 2247 void Assembler::movdqa(XMMRegister dst, const Operand& src) { |
2216 ASSERT(CpuFeatures::IsEnabled(SSE2)); | 2248 ASSERT(CpuFeatures::IsEnabled(SSE2)); |
2217 EnsureSpace ensure_space(this); | 2249 EnsureSpace ensure_space(this); |
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2351 ASSERT(CpuFeatures::IsEnabled(SSE2)); | 2383 ASSERT(CpuFeatures::IsEnabled(SSE2)); |
2352 EnsureSpace ensure_space(this); | 2384 EnsureSpace ensure_space(this); |
2353 last_pc_ = pc_; | 2385 last_pc_ = pc_; |
2354 EMIT(0x66); | 2386 EMIT(0x66); |
2355 EMIT(0x0F); | 2387 EMIT(0x0F); |
2356 EMIT(0x38); | 2388 EMIT(0x38); |
2357 EMIT(0x17); | 2389 EMIT(0x17); |
2358 emit_sse_operand(dst, src); | 2390 emit_sse_operand(dst, src); |
2359 } | 2391 } |
2360 | 2392 |
| 2393 |
| 2394 void Assembler::psllq(XMMRegister reg, int8_t imm8) { |
| 2395 ASSERT(CpuFeatures::IsEnabled(SSE2)); |
| 2396 EnsureSpace ensure_space(this); |
| 2397 last_pc_ = pc_; |
| 2398 EMIT(0x66); |
| 2399 EMIT(0x0F); |
| 2400 EMIT(0x73); |
| 2401 emit_sse_operand(esi, reg); // esi == 6 |
| 2402 EMIT(imm8); |
| 2403 } |
| 2404 |
| 2405 |
2361 void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) { | 2406 void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) { |
2362 Register ireg = { reg.code() }; | 2407 Register ireg = { reg.code() }; |
2363 emit_operand(ireg, adr); | 2408 emit_operand(ireg, adr); |
2364 } | 2409 } |
2365 | 2410 |
2366 | 2411 |
2367 void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) { | 2412 void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) { |
2368 EMIT(0xC0 | dst.code() << 3 | src.code()); | 2413 EMIT(0xC0 | dst.code() << 3 | src.code()); |
2369 } | 2414 } |
2370 | 2415 |
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2612 fprintf(coverage_log, "%s\n", file_line); | 2657 fprintf(coverage_log, "%s\n", file_line); |
2613 fflush(coverage_log); | 2658 fflush(coverage_log); |
2614 } | 2659 } |
2615 } | 2660 } |
2616 | 2661 |
2617 #endif | 2662 #endif |
2618 | 2663 |
2619 } } // namespace v8::internal | 2664 } } // namespace v8::internal |
2620 | 2665 |
2621 #endif // V8_TARGET_ARCH_IA32 | 2666 #endif // V8_TARGET_ARCH_IA32 |
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