[gcc] Fix addsi patterns for nacl64 PIC

gcc/gcc/config/i386/i386.md

Index: gcc/gcc/config/i386/i386.md
diff --git a/gcc/gcc/config/i386/i386.md b/gcc/gcc/config/i386/i386.md
index e00d5a97526bf0357ed0da8c2a9ae7b0507fad61..ddf9e9c2b98308bdb28f6c8b186bbbcf7f1c5ef8 100644
--- a/gcc/gcc/config/i386/i386.md
+++ b/gcc/gcc/config/i386/i386.md
@@ -5930,7 +5930,7 @@
 	  (zero_extend:DI
 	    (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
 			      (match_operand:SI 1 "nonimmediate_operand" "%0"))
-		     (match_operand:SI 2 "general_operand" "g"))))
+		     (match_operand:SI 2 "x86_64_general_operand" "rem"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
   "adc{l}\t{%2, %k0|%k0, %2}"
@@ -5941,7 +5941,7 @@
 (define_insn "*addsi3_cc"
   [(set (reg:CC FLAGS_REG)
 	(unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
-		    (match_operand:SI 2 "general_operand" "ri,rm")]
+		    (match_operand:SI 2 "x86_64_general_operand" "re,rm")]
 		   UNSPEC_ADD_CARRY))
    (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
 	(plus:SI (match_dup 1) (match_dup 2)))]
@@ -5965,7 +5965,7 @@
 (define_expand "addsi3"
   [(set (match_operand:SI 0 "nonimmediate_operand" "")
 	(plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
-		 (match_operand:SI 2 "general_operand" "")))]
+		 (match_operand:SI 2 "x86_64_general_operand" "")))]
   ""
   "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
 
@@ -6495,7 +6495,7 @@
 (define_insn "*addsi_1"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
 	(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
-		 (match_operand:SI 2 "general_operand" "g,re,le")))
+		 (match_operand:SI 2 "x86_64_general_operand" "rme,re,le")))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (PLUS, SImode, operands)"
 {
@@ -6659,7 +6659,7 @@
   [(set (reg FLAGS_REG)
 	(compare
 	  (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
-		   (match_operand:SI 2 "general_operand" "g,ri"))
+		   (match_operand:SI 2 "x86_64_general_operand" "rem,ri"))
 	  (const_int 0)))
    (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
 	(plus:SI (match_dup 1) (match_dup 2)))]
@@ -6707,7 +6707,7 @@
   [(set (reg FLAGS_REG)
 	(compare
 	  (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-		   (match_operand:SI 2 "general_operand" "g"))
+		   (match_operand:SI 2 "x86_64_general_operand" "rem"))
 	  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
@@ -6750,7 +6750,7 @@
 
 (define_insn "*addsi_3"
   [(set (reg FLAGS_REG)
-	(compare (neg:SI (match_operand:SI 2 "general_operand" "g"))
+	(compare (neg:SI (match_operand:SI 2 "x86_64_general_operand" "rem"))
 		 (match_operand:SI 1 "nonimmediate_operand" "%0")))
    (clobber (match_scratch:SI 0 "=r"))]
   "ix86_match_ccmode (insn, CCZmode)
@@ -6795,7 +6795,7 @@
 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
 (define_insn "*addsi_3_zext"
   [(set (reg FLAGS_REG)
-	(compare (neg:SI (match_operand:SI 2 "general_operand" "g"))
+	(compare (neg:SI (match_operand:SI 2 "x86_64_general_operand" "rem"))
 		 (match_operand:SI 1 "nonimmediate_operand" "%0")))
    (set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
@@ -6885,7 +6885,7 @@
   [(set (reg FLAGS_REG)
 	(compare
 	  (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-		   (match_operand:SI 2 "general_operand" "g"))
+		   (match_operand:SI 2 "x86_64_general_operand" "rem"))
 	  (const_int 0)))
    (clobber (match_scratch:SI 0 "=r"))]
   "ix86_match_ccmode (insn, CCGOCmode)