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1 // Copyright 2010 the V8 project authors. All rights reserved. | 1 // Copyright 2010 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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599 registers_[reg] = (reg == 0) ? 0 : value; | 599 registers_[reg] = (reg == 0) ? 0 : value; |
600 } | 600 } |
601 | 601 |
602 void Simulator::set_fpu_register(int fpureg, int32_t value) { | 602 void Simulator::set_fpu_register(int fpureg, int32_t value) { |
603 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); | 603 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
604 FPUregisters_[fpureg] = value; | 604 FPUregisters_[fpureg] = value; |
605 } | 605 } |
606 | 606 |
607 void Simulator::set_fpu_register_double(int fpureg, double value) { | 607 void Simulator::set_fpu_register_double(int fpureg, double value) { |
608 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0)); | 608 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0)); |
609 *v8i::BitCast<double*, int32_t*>(&FPUregisters_[fpureg]) = value; | 609 *v8i::BitCast<double*>(&FPUregisters_[fpureg]) = value; |
610 } | 610 } |
611 | 611 |
612 | 612 |
613 // Get the register from the architecture state. This function does handle | 613 // Get the register from the architecture state. This function does handle |
614 // the special case of accessing the PC register. | 614 // the special case of accessing the PC register. |
615 int32_t Simulator::get_register(int reg) const { | 615 int32_t Simulator::get_register(int reg) const { |
616 ASSERT((reg >= 0) && (reg < kNumSimuRegisters)); | 616 ASSERT((reg >= 0) && (reg < kNumSimuRegisters)); |
617 if (reg == 0) | 617 if (reg == 0) |
618 return 0; | 618 return 0; |
619 else | 619 else |
620 return registers_[reg] + ((reg == pc) ? Instruction::kPCReadOffset : 0); | 620 return registers_[reg] + ((reg == pc) ? Instruction::kPCReadOffset : 0); |
621 } | 621 } |
622 | 622 |
623 int32_t Simulator::get_fpu_register(int fpureg) const { | 623 int32_t Simulator::get_fpu_register(int fpureg) const { |
624 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); | 624 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters)); |
625 return FPUregisters_[fpureg]; | 625 return FPUregisters_[fpureg]; |
626 } | 626 } |
627 | 627 |
628 double Simulator::get_fpu_register_double(int fpureg) const { | 628 double Simulator::get_fpu_register_double(int fpureg) const { |
629 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0)); | 629 ASSERT((fpureg >= 0) && (fpureg < kNumFPURegisters) && ((fpureg % 2) == 0)); |
630 return *v8i::BitCast<double*, int32_t*>( | 630 return *v8i::BitCast<double*>(const_cast<int32_t*>(&FPUregisters_[fpureg])); |
631 const_cast<int32_t*>(&FPUregisters_[fpureg])); | |
632 } | 631 } |
633 | 632 |
634 // Raw access to the PC register. | 633 // Raw access to the PC register. |
635 void Simulator::set_pc(int32_t value) { | 634 void Simulator::set_pc(int32_t value) { |
636 pc_modified_ = true; | 635 pc_modified_ = true; |
637 registers_[pc] = value; | 636 registers_[pc] = value; |
638 } | 637 } |
639 | 638 |
640 // Raw access to the PC register without the special adjustment when reading. | 639 // Raw access to the PC register without the special adjustment when reading. |
641 int32_t Simulator::get_pc() const { | 640 int32_t Simulator::get_pc() const { |
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896 case COP1: // Coprocessor instructions | 895 case COP1: // Coprocessor instructions |
897 switch (instr->RsFieldRaw()) { | 896 switch (instr->RsFieldRaw()) { |
898 case BC1: // branch on coprocessor condition | 897 case BC1: // branch on coprocessor condition |
899 UNREACHABLE(); | 898 UNREACHABLE(); |
900 break; | 899 break; |
901 case MFC1: | 900 case MFC1: |
902 alu_out = get_fpu_register(fs_reg); | 901 alu_out = get_fpu_register(fs_reg); |
903 break; | 902 break; |
904 case MFHC1: | 903 case MFHC1: |
905 fp_out = get_fpu_register_double(fs_reg); | 904 fp_out = get_fpu_register_double(fs_reg); |
906 alu_out = *v8i::BitCast<int32_t*, double*>(&fp_out); | 905 alu_out = *v8i::BitCast<int32_t*>(&fp_out); |
907 break; | 906 break; |
908 case MTC1: | 907 case MTC1: |
909 case MTHC1: | 908 case MTHC1: |
910 // Do the store in the execution step. | 909 // Do the store in the execution step. |
911 break; | 910 break; |
912 case S: | 911 case S: |
913 case D: | 912 case D: |
914 case W: | 913 case W: |
915 case L: | 914 case L: |
916 case PS: | 915 case PS: |
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1642 } | 1641 } |
1643 | 1642 |
1644 | 1643 |
1645 #undef UNSUPPORTED | 1644 #undef UNSUPPORTED |
1646 | 1645 |
1647 } } // namespace assembler::mips | 1646 } } // namespace assembler::mips |
1648 | 1647 |
1649 #endif // __mips | 1648 #endif // __mips |
1650 | 1649 |
1651 #endif // V8_TARGET_ARCH_MIPS | 1650 #endif // V8_TARGET_ARCH_MIPS |
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