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Unified Diff: test/cctest/test-disasm-arm.cc

Issue 3107027: Fix incorrect encoding of single and double precision registers for some... (Closed) Base URL: http://v8.googlecode.com/svn/branches/bleeding_edge/
Patch Set: '' Created 10 years, 4 months ago
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Index: test/cctest/test-disasm-arm.cc
===================================================================
--- test/cctest/test-disasm-arm.cc (revision 5347)
+++ test/cctest/test-disasm-arm.cc (working copy)
@@ -422,6 +422,19 @@
COMPARE(vmov(d3, d3, eq),
"0eb03b43 vmov.f64eq d3, d3");
+ COMPARE(vmov(s0, s31),
+ "eeb00a6f vmov.f32 s0, s31");
+ COMPARE(vmov(s31, s0),
+ "eef0fa40 vmov.f32 s31, s0");
+ COMPARE(vmov(r0, s0),
+ "ee100a10 vmov r0, s0");
+ COMPARE(vmov(r10, s31),
+ "ee1faa90 vmov r10, s31");
+ COMPARE(vmov(s0, r0),
+ "ee000a10 vmov s0, r0");
+ COMPARE(vmov(s31, r10),
+ "ee0faa90 vmov s31, r10");
+
COMPARE(vadd(d0, d1, d2),
"ee310b02 vadd.f64 d0, d1, d2");
COMPARE(vadd(d3, d4, d5, mi),
@@ -451,6 +464,41 @@
"eeb70b00 vmov.f64 d0, #1");
COMPARE(vmov(d2, -13.0),
"eeba2b0a vmov.f64 d2, #-13");
+
+ COMPARE(vldr(s0, r0, 0),
+ "ed900a00 vldr s0, [r0 + 4*0]");
+ COMPARE(vldr(s1, r1, 4),
+ "edd10a01 vldr s1, [r1 + 4*1]");
+ COMPARE(vldr(s15, r4, 16),
+ "edd47a04 vldr s15, [r4 + 4*4]");
+ COMPARE(vldr(s16, r5, 20),
+ "ed958a05 vldr s16, [r5 + 4*5]");
+ COMPARE(vldr(s31, r10, 1020),
+ "eddafaff vldr s31, [r10 + 4*255]");
+
+ COMPARE(vstr(s0, r0, 0),
+ "ed800a00 vstr s0, [r0 + 4*0]");
+ COMPARE(vstr(s1, r1, 4),
+ "edc10a01 vstr s1, [r1 + 4*1]");
+ COMPARE(vstr(s15, r8, 8),
+ "edc87a02 vstr s15, [r8 + 4*2]");
+ COMPARE(vstr(s16, r9, 12),
+ "ed898a03 vstr s16, [r9 + 4*3]");
+ COMPARE(vstr(s31, r10, 1020),
+ "edcafaff vstr s31, [r10 + 4*255]");
+
+ COMPARE(vldr(d0, r0, 0),
+ "ed900b00 vldr d0, [r0 + 4*0]");
+ COMPARE(vldr(d1, r1, 4),
+ "ed911b01 vldr d1, [r1 + 4*1]");
+ COMPARE(vldr(d15, r10, 1020),
+ "ed9afbff vldr d15, [r10 + 4*255]");
+ COMPARE(vstr(d0, r0, 0),
+ "ed800b00 vstr d0, [r0 + 4*0]");
+ COMPARE(vstr(d1, r1, 4),
+ "ed811b01 vstr d1, [r1 + 4*1]");
+ COMPARE(vstr(d15, r10, 1020),
+ "ed8afbff vstr d15, [r10 + 4*255]");
}
VERIFY_RUN();
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