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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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113 Address RelocInfo::call_address() { | 113 Address RelocInfo::call_address() { |
114 // The 2 instructions offset assumes patched debug break slot or return | 114 // The 2 instructions offset assumes patched debug break slot or return |
115 // sequence. | 115 // sequence. |
116 ASSERT((IsJSReturn(rmode()) && IsPatchedReturnSequence()) || | 116 ASSERT((IsJSReturn(rmode()) && IsPatchedReturnSequence()) || |
117 (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence())); | 117 (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence())); |
118 return Memory::Address_at(pc_ + 2 * Assembler::kInstrSize); | 118 return Memory::Address_at(pc_ + 2 * Assembler::kInstrSize); |
119 } | 119 } |
120 | 120 |
121 | 121 |
122 void RelocInfo::set_call_address(Address target) { | 122 void RelocInfo::set_call_address(Address target) { |
123 ASSERT(IsPatchedReturnSequence()); | 123 ASSERT((IsJSReturn(rmode()) && IsPatchedReturnSequence()) || |
124 // The 2 instructions offset assumes patched return sequence. | 124 (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence())); |
125 ASSERT(IsJSReturn(rmode())); | |
126 Memory::Address_at(pc_ + 2 * Assembler::kInstrSize) = target; | 125 Memory::Address_at(pc_ + 2 * Assembler::kInstrSize) = target; |
127 } | 126 } |
128 | 127 |
129 | 128 |
130 Object* RelocInfo::call_object() { | 129 Object* RelocInfo::call_object() { |
131 return *call_object_address(); | 130 return *call_object_address(); |
132 } | 131 } |
133 | 132 |
134 | 133 |
135 Object** RelocInfo::call_object_address() { | |
136 ASSERT(IsPatchedReturnSequence()); | |
137 // The 2 instructions offset assumes patched return sequence. | |
138 ASSERT(IsJSReturn(rmode())); | |
139 return reinterpret_cast<Object**>(pc_ + 2 * Assembler::kInstrSize); | |
140 } | |
141 | |
142 | |
143 void RelocInfo::set_call_object(Object* target) { | 134 void RelocInfo::set_call_object(Object* target) { |
144 *call_object_address() = target; | 135 *call_object_address() = target; |
145 } | 136 } |
146 | 137 |
147 | 138 |
| 139 Object** RelocInfo::call_object_address() { |
| 140 ASSERT((IsJSReturn(rmode()) && IsPatchedReturnSequence()) || |
| 141 (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence())); |
| 142 return reinterpret_cast<Object**>(pc_ + 2 * Assembler::kInstrSize); |
| 143 } |
| 144 |
| 145 |
148 bool RelocInfo::IsPatchedReturnSequence() { | 146 bool RelocInfo::IsPatchedReturnSequence() { |
149 Instr current_instr = Assembler::instr_at(pc_); | 147 Instr current_instr = Assembler::instr_at(pc_); |
150 Instr next_instr = Assembler::instr_at(pc_ + Assembler::kInstrSize); | 148 Instr next_instr = Assembler::instr_at(pc_ + Assembler::kInstrSize); |
151 #ifdef USE_BLX | 149 #ifdef USE_BLX |
152 // A patched return sequence is: | 150 // A patched return sequence is: |
153 // ldr ip, [pc, #0] | 151 // ldr ip, [pc, #0] |
154 // blx ip | 152 // blx ip |
155 return ((current_instr & kLdrPCMask) == kLdrPCPattern) | 153 return ((current_instr & kLdrPCMask) == kLdrPCPattern) |
156 && ((next_instr & kBlxRegMask) == kBlxRegPattern); | 154 && ((next_instr & kBlxRegMask) == kBlxRegPattern); |
157 #else | 155 #else |
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296 // CPU::FlushICache(pc, sizeof(target)); | 294 // CPU::FlushICache(pc, sizeof(target)); |
297 // However, on ARM, no instruction was actually patched by the assignment | 295 // However, on ARM, no instruction was actually patched by the assignment |
298 // above; the target address is not part of an instruction, it is patched in | 296 // above; the target address is not part of an instruction, it is patched in |
299 // the constant pool and is read via a data access; the instruction accessing | 297 // the constant pool and is read via a data access; the instruction accessing |
300 // this address in the constant pool remains unchanged. | 298 // this address in the constant pool remains unchanged. |
301 } | 299 } |
302 | 300 |
303 } } // namespace v8::internal | 301 } } // namespace v8::internal |
304 | 302 |
305 #endif // V8_ARM_ASSEMBLER_ARM_INL_H_ | 303 #endif // V8_ARM_ASSEMBLER_ARM_INL_H_ |
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