[gcc] GCC 4.5.0=>4.5.1

gcc/gcc/config/s390/2064.md

Index: gcc/gcc/config/s390/2064.md
diff --git a/gcc/gcc/config/s390/2064.md b/gcc/gcc/config/s390/2064.md
index 573826a75494e62c57b1f51d70b0f1afad87755c..143978334a31a42418e2d09e4df06d40fc2bd6f7 100644
--- a/gcc/gcc/config/s390/2064.md
+++ b/gcc/gcc/config/s390/2064.md
@@ -21,22 +21,22 @@
 
 ;;
 ;; References:
-;;   The microarchitecture of the IBM eServer z900 processor. 
+;;   The microarchitecture of the IBM eServer z900 processor.
 ;;   E.M. Schwarz et al.
 ;;   IBM Journal of Research and Development Vol. 46 No 4/5, 2002.
-;; 
+;;
 ;;            z900 (cpu 2064) pipeline
-;;     
+;;
 ;;                 dec
 ;;              --> | <---
 ;;  LA bypass  |  agen    |
-;;             |    |     | 
+;;             |    |     |
 ;;              --- c1    |  Load bypass
-;;                  |     | 
+;;                  |     |
 ;;                  c2----
 ;;                  |
-;;                  e1 
-;;                  | 
+;;                  e1
+;;                  |
 ;;                  wr
 
 ;; This scheduler description is also used for the g5 and g6.
@@ -46,12 +46,12 @@
 (define_cpu_unit "z_wr"   "z_ipu")
 
 
-(define_insn_reservation "z_la" 1 
+(define_insn_reservation "z_la" 1
   (and (eq_attr "cpu" "z900,g5,g6")
        (eq_attr "type" "la"))
   "z_e1,z_wr")
 
-(define_insn_reservation "z_larl" 1 
+(define_insn_reservation "z_larl" 1
   (and (eq_attr "cpu" "z900,g5,g6")
        (eq_attr "type" "larl"))
   "z_e1,z_wr")
@@ -101,32 +101,32 @@
   "z_e1,z_wr")
 
 ;;
-;; s390_agen_dep_p returns 1, if a register is set in the 
+;; s390_agen_dep_p returns 1, if a register is set in the
 ;; first insn and used in the dependent insn to form a address.
 ;;
 
 ;;
 ;; If an instruction uses a register to address memory, it needs
 ;; to be set 5 cycles in advance.
-;; 
+;;
 
-(define_bypass 5 "z_int,z_agen" 
+(define_bypass 5 "z_int,z_agen"
 	       "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
 
 ;;
-;; A load type instruction uses a bypass to feed the result back	
-;; to the address generation pipeline stage. 
+;; A load type instruction uses a bypass to feed the result back
+;; to the address generation pipeline stage.
 ;;
 
-(define_bypass 3 "z_load"    
+(define_bypass 3 "z_load"
 	         "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
 
 ;;
-;; A load address type instruction uses a bypass to feed the 
-;; result back to the address generation pipeline stage. 
+;; A load address type instruction uses a bypass to feed the
+;; result back to the address generation pipeline stage.
 ;;
 
-(define_bypass 2 "z_larl,z_la" 
+(define_bypass 2 "z_larl,z_la"
 	         "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")