[gcc] GCC 4.5.0=>4.5.1

gcc/gcc/config/rs6000/power5.md

Index: gcc/gcc/config/rs6000/power5.md
diff --git a/gcc/gcc/config/rs6000/power5.md b/gcc/gcc/config/rs6000/power5.md
index 1b73e093e6ed77d42446cc96be2c2cdf0ad893f4..b6db0931219d993c54bf6870a487fbd0a1646788 100644
--- a/gcc/gcc/config/rs6000/power5.md
+++ b/gcc/gcc/config/rs6000/power5.md
@@ -1,5 +1,5 @@
 ;; Scheduling description for IBM POWER5 processor.
-;;   Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
+;;   Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
 ;;
@@ -40,16 +40,12 @@
 		    |(du4_power5,lsu1_power5)")
 
 (define_reservation "iq_power5"
-		    "(du1_power5,iu1_power5)\
-		    |(du2_power5,iu2_power5)\
-		    |(du3_power5,iu2_power5)\
-		    |(du4_power5,iu1_power5)")
+		    "(du1_power5|du2_power5|du3_power5|du4_power5),\
+                     (iu1_power5|iu2_power5)")
 
 (define_reservation "fpq_power5"
-		    "(du1_power5,fpu1_power5)\
-		    |(du2_power5,fpu2_power5)\
-		    |(du3_power5,fpu2_power5)\
-		    |(du4_power5,fpu1_power5)")
+		    "(du1_power5|du2_power5|du3_power5|du4_power5),\
+                     (fpu1_power5|fpu2_power5)")
 
 ; Dispatch slots are allocated in order conforming to program order.
 (absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5")
@@ -105,10 +101,11 @@
 (define_insn_reservation "power5-store" 12
   (and (eq_attr "type" "store")
        (eq_attr "cpu" "power5"))
-  "(du1_power5,lsu1_power5,iu1_power5)\
-  |(du2_power5,lsu2_power5,iu2_power5)\
-  |(du3_power5,lsu2_power5,iu2_power5)\
-  |(du4_power5,lsu1_power5,iu1_power5)")
+  "((du1_power5,lsu1_power5)\
+    |(du2_power5,lsu2_power5)\
+    |(du3_power5,lsu2_power5)\
+    |(du4_power5,lsu1_power5)),\
+    (iu1_power5|iu2_power5)")
 
 (define_insn_reservation "power5-store-update" 12
   (and (eq_attr "type" "store_u")
@@ -124,10 +121,11 @@
 (define_insn_reservation "power5-fpstore" 12
   (and (eq_attr "type" "fpstore")
        (eq_attr "cpu" "power5"))
-  "(du1_power5,lsu1_power5,fpu1_power5)\
-  |(du2_power5,lsu2_power5,fpu2_power5)\
-  |(du3_power5,lsu2_power5,fpu2_power5)\
-  |(du4_power5,lsu1_power5,fpu1_power5)")
+  "((du1_power5,lsu1_power5)\
+    |(du2_power5,lsu2_power5)\
+    |(du3_power5,lsu2_power5)\
+    |(du4_power5,lsu1_power5)),\
+    (fpu1_power5|fpu2_power5)")
 
 (define_insn_reservation "power5-fpstore-update" 12
   (and (eq_attr "type" "fpstore_u,fpstore_ux")
@@ -144,29 +142,31 @@
 ; Integer latency is 2 cycles
 (define_insn_reservation "power5-integer" 2
   (and (eq_attr "type" "integer,insert_dword,shift,trap,\
-                        var_shift_rotate,cntlz,exts")
+                        var_shift_rotate,cntlz,exts,isel")
        (eq_attr "cpu" "power5"))
   "iq_power5")
 
 (define_insn_reservation "power5-two" 2
   (and (eq_attr "type" "two")
        (eq_attr "cpu" "power5"))
-  "(du1_power5+du2_power5,iu1_power5,nothing,iu2_power5)\
-  |(du2_power5+du3_power5,iu2_power5,nothing,iu2_power5)\
-  |(du3_power5+du4_power5,iu2_power5,nothing,iu1_power5)\
-  |(du4_power5+du1_power5,iu1_power5,nothing,iu1_power5)")
+  "((du1_power5+du2_power5)\
+    |(du2_power5+du3_power5)\
+    |(du3_power5+du4_power5)\
+    |(du4_power5+du1_power5)),\
+    ((iu1_power5,nothing,iu2_power5)\
+     |(iu2_power5,nothing,iu2_power5)\
+     |(iu2_power5,nothing,iu1_power5)\
+     |(iu1_power5,nothing,iu1_power5))")
 
 (define_insn_reservation "power5-three" 2
   (and (eq_attr "type" "three")
        (eq_attr "cpu" "power5"))
-  "(du1_power5+du2_power5+du3_power5,\
-    iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\
-  |(du2_power5+du3_power5+du4_power5,\
-    iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\
-  |(du3_power5+du4_power5+du1_power5,\
-    iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\
-  |(du4_power5+du1_power5+du2_power5,\
-    iu1_power5,nothing,iu2_power5,nothing,iu2_power5)")
+  "(du1_power5+du2_power5+du3_power5|du2_power5+du3_power5+du4_power5\
+    |du3_power5+du4_power5+du1_power5|du4_power5+du1_power5+du2_power5),\
+   ((iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\
+    |(iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\
+    |(iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\
+    |(iu1_power5,nothing,iu2_power5,nothing,iu2_power5))")
 
 (define_insn_reservation "power5-insert" 4
   (and (eq_attr "type" "insert_word")
@@ -202,26 +202,17 @@
 (define_insn_reservation "power5-lmul" 7
   (and (eq_attr "type" "lmul")
        (eq_attr "cpu" "power5"))
-  "(du1_power5,iu1_power5*6)\
-  |(du2_power5,iu2_power5*6)\
-  |(du3_power5,iu2_power5*6)\
-  |(du4_power5,iu1_power5*6)")
+  "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*6|iu2_power5*6)")
 
 (define_insn_reservation "power5-imul" 5
   (and (eq_attr "type" "imul")
        (eq_attr "cpu" "power5"))
-  "(du1_power5,iu1_power5*4)\
-  |(du2_power5,iu2_power5*4)\
-  |(du3_power5,iu2_power5*4)\
-  |(du4_power5,iu1_power5*4)")
+  "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*4|iu2_power5*4)")
 
 (define_insn_reservation "power5-imul3" 4
   (and (eq_attr "type" "imul2,imul3")
        (eq_attr "cpu" "power5"))
-  "(du1_power5,iu1_power5*3)\
-  |(du2_power5,iu2_power5*3)\
-  |(du3_power5,iu2_power5*3)\
-  |(du4_power5,iu1_power5*3)")
+  "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*3|iu2_power5*3)")
 
 
 ; SPR move only executes in first IU.
@@ -300,18 +291,14 @@
 (define_insn_reservation "power5-sdiv" 33
   (and (eq_attr "type" "sdiv,ddiv")
        (eq_attr "cpu" "power5"))
-  "(du1_power5,fpu1_power5*28)\
-  |(du2_power5,fpu2_power5*28)\
-  |(du3_power5,fpu2_power5*28)\
-  |(du4_power5,fpu1_power5*28)")
+  "(du1_power5|du2_power5|du3_power5|du4_power5),\
+   (fpu1_power5*28|fpu2_power5*28)")
 
 (define_insn_reservation "power5-sqrt" 40
   (and (eq_attr "type" "ssqrt,dsqrt")
        (eq_attr "cpu" "power5"))
-  "(du1_power5,fpu1_power5*35)\
-  |(du2_power5,fpu2_power5*35)\
-  |(du3_power5,fpu2_power5*35)\
-  |(du4_power5,fpu2_power5*35)")
+  "(du1_power5|du2_power5|du3_power5|du4_power5),\
+   (fpu1_power5*35|fpu2_power5*35)")
 
 (define_insn_reservation "power5-isync" 2 
   (and (eq_attr "type" "isync")