gcc/gcc/config/i386/i386.h - Issue 3050029: [gcc] GCC 4.5.0=>4.5.1

Unified Diff: gcc/gcc/config/i386/i386.h

Issue 3050029: [gcc] GCC 4.5.0=>4.5.1 (Closed) Base URL: ssh://git@gitrw.chromium.org:9222/nacl-toolchain.git

Patch Set: Created 10 years, 5 months ago

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Index: gcc/gcc/config/i386/i386.h

diff --git a/gcc/gcc/config/i386/i386.h b/gcc/gcc/config/i386/i386.h

index 23c0d183eef9a8b69a0b6df6ff70911c87d83334..5bae99d9dbbe18581f9a5a22f0fe0842f7212a34 100644

--- a/gcc/gcc/config/i386/i386.h

+++ b/gcc/gcc/config/i386/i386.h

@@ -1,6 +1,6 @@

/* Definitions of target machine for GCC for IA-32.

- 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009

+ 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010

Free Software Foundation, Inc.

This file is part of GCC.

@@ -54,18 +54,22 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see

#define TARGET_AVX OPTION_ISA_AVX

#define TARGET_FMA OPTION_ISA_FMA

#define TARGET_SSE4A OPTION_ISA_SSE4A

-#define TARGET_SSE5 OPTION_ISA_SSE5

+#define TARGET_FMA4 OPTION_ISA_FMA4

+#define TARGET_XOP OPTION_ISA_XOP

+#define TARGET_LWP OPTION_ISA_LWP

#define TARGET_ROUND OPTION_ISA_ROUND

#define TARGET_ABM OPTION_ISA_ABM

#define TARGET_POPCNT OPTION_ISA_POPCNT

#define TARGET_SAHF OPTION_ISA_SAHF

+#define TARGET_MOVBE OPTION_ISA_MOVBE

+#define TARGET_CRC32 OPTION_ISA_CRC32

#define TARGET_AES OPTION_ISA_AES

#define TARGET_PCLMUL OPTION_ISA_PCLMUL

#define TARGET_CMPXCHG16B OPTION_ISA_CX16

-/* SSE5 and SSE4.1 define the same round instructions */

-#define OPTION_MASK_ISA_ROUND (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE5)

+/* SSE4.1 defines round instructions */

+#define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1

#define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0)

#include "config/vxworks-dummy.h"

@@ -236,6 +240,7 @@ extern const struct processor_costs ix86_size_cost;

#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)

#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)

#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)

+#define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)

/* Feature tests against the various tunings. */

enum ix86_tune_indices {

@@ -300,6 +305,7 @@ enum ix86_tune_indices {

X86_TUNE_USE_VECTOR_FP_CONVERTS,

X86_TUNE_USE_VECTOR_CONVERTS,

X86_TUNE_FUSE_CMP_AND_BRANCH,

+ X86_TUNE_OPT_AGU,

X86_TUNE_LAST

};

@@ -387,6 +393,7 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST];

ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]

#define TARGET_FUSE_CMP_AND_BRANCH \

ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH]

+#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]

/* Feature tests against the various architecture variations. */

enum ix86_arch_indices {

@@ -422,7 +429,7 @@ extern int x86_prefetch_sse;

#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)

#define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)

#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)

-#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)

+#define TARGET_SUN_TLS 0

extern int ix86_isa_flags;

@@ -470,7 +477,10 @@ enum calling_abi

MS_ABI = 1

};

-/* The default abi form used by target. */

+/* The abi used by target. */

+extern enum calling_abi ix86_abi;

+/* The default abi used by target. */

#define DEFAULT_ABI SYSV_ABI

/* Subtargets may reset this to 1 in order to enable 96-bit long double

@@ -534,6 +544,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);

%<mcpu=* \

%{mintel-syntax:-masm=intel \

%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \

+%{msse5:-mavx \

+%n'-msse5' was removed.\n} \

%{mno-intel-syntax:-masm=att \

%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"

@@ -569,6 +581,7 @@ enum target_cpu_default

TARGET_CPU_DEFAULT_prescott,

TARGET_CPU_DEFAULT_nocona,

TARGET_CPU_DEFAULT_core2,

+ TARGET_CPU_DEFAULT_atom,

TARGET_CPU_DEFAULT_geode,

TARGET_CPU_DEFAULT_k6,

@@ -613,6 +626,20 @@ enum target_cpu_default

#define TARGET_FLT_EVAL_METHOD \

(TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)

+/* Whether to allow x87 floating-point arithmetic on MODE (one of

+ SFmode, DFmode and XFmode) in the current excess precision

+ configuration. */

+#define X87_ENABLE_ARITH(MODE) \

+ (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode)

+/* Likewise, whether to allow direct conversions from integer mode

+ IMODE (HImode, SImode or DImode) to MODE. */

+#define X87_ENABLE_FLOAT(MODE, IMODE) \

+ (flag_excess_precision == EXCESS_PRECISION_FAST \

+ || (MODE) == XFmode \

+ || ((MODE) == DFmode && (IMODE) == SImode) \

+ || (IMODE) == HImode)

/* target machine storage layout */

#define SHORT_TYPE_SIZE 16

@@ -658,7 +685,7 @@ enum target_cpu_default

/* Boundary (in *bits*) on which stack pointer should be aligned. */

#define STACK_BOUNDARY \

- (TARGET_64BIT && DEFAULT_ABI == MS_ABI ? 128 : BITS_PER_WORD)

+ (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD)

/* Stack boundary of the main function guaranteed by OS. */

#define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)

@@ -679,9 +706,7 @@ enum target_cpu_default

generate an alternate prologue and epilogue that realigns the

runtime stack if nessary. This supports mixing codes that keep a

4-byte aligned stack, as specified by i386 psABI, with codes that

- need a 16-byte aligned stack, as required by SSE instructions. If

- STACK_REALIGN_DEFAULT is 1 and PREFERRED_STACK_BOUNDARY_DEFAULT is

- 128, stacks for all functions may be realigned. */

+ need a 16-byte aligned stack, as required by SSE instructions. */

#define STACK_REALIGN_DEFAULT 0

/* Boundary (in *bits*) on which the incoming stack is aligned. */

@@ -846,6 +871,9 @@ enum target_cpu_default

|| ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \

|| (MODE) == XFmode)

+/* Cover class containing the stack registers. */

+#define STACK_REG_COVER_CLASS FLOAT_REGS

/* Number of actual hardware registers.

The hardware registers are assigned numbers for the compiler

from 0 to just below FIRST_PSEUDO_REGISTER.

@@ -985,7 +1013,8 @@ enum target_cpu_default

|| (MODE) == V2DImode || (MODE) == DFmode)

#define VALID_SSE_REG_MODE(MODE) \

- ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \

+ ((MODE) == V1TImode || (MODE) == TImode \

+ || (MODE) == V4SFmode || (MODE) == V4SImode \

|| (MODE) == SFmode || (MODE) == TFmode)

#define VALID_MMX_REG_MODE_3DNOW(MODE) \

@@ -1023,11 +1052,11 @@ enum target_cpu_default

/* Return true for modes passed in SSE registers. */

#define SSE_REG_MODE_P(MODE) \

- ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \

- || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \

- || (MODE) == V4SFmode || (MODE) == V4SImode || (MODE) == V32QImode \

- || (MODE) == V16HImode || (MODE) == V8SImode || (MODE) == V4DImode \

- || (MODE) == V8SFmode || (MODE) == V4DFmode)

+ ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \

+ || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \

+ || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \

+ || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \

+ || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode)

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */

@@ -1093,12 +1122,6 @@ enum target_cpu_default

#define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)

#define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)

-/* Value should be nonzero if functions must have frame pointers.

- Zero means the frame pointer need not be set up (and parms

- may be accessed via the stack pointer) in functions that seem suitable.

- This is computed in `reload', in reload1.c. */

-#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()

/* Override this in other tm.h files to cope with various OS lossage

requiring a frame pointer. */

#ifndef SUBTARGET_FRAME_POINTER_REQUIRED

@@ -1111,11 +1134,6 @@ enum target_cpu_default

/* Base register for access to arguments of the function. */

#define ARG_POINTER_REGNUM 16

-/* Register in which static-chain is passed to a function.

- We do use ECX as static chain register for 32 bit ABI. On the

- 64bit ABI, ECX is an argument register, so we use R10 instead. */

-#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? R10_REG : CX_REG)

/* Register to hold the addressing base for position independent

code access to data items. We don't use PIC pointer for 64bit

mode. Define the regnum to dummy value to prevent gcc from

@@ -1271,19 +1289,6 @@ enum reg_class

{ 0xffffffff,0x1fffff } \

}

-/* The following macro defines cover classes for Integrated Register

- Allocator. Cover classes is a set of non-intersected register

- classes covering all hard registers used for register allocation

- purpose. Any move between two registers of a cover class should be

- cheaper than load or store of the registers. The macro value is

- array of register classes with LIM_REG_CLASSES used as the end

- marker. */

-#define IRA_COVER_CLASSES \

-{ \

- GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES \

/* The same information, inverted:

Return the class number of the smallest class containing

reg number REGNO. This could be a conditional expression

@@ -1349,6 +1354,10 @@ enum reg_class

(TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode \

|| (MODE) == V8SFmode || (MODE) == V4DFmode))

+#define FMA4_VEC_FLOAT_MODE_P(MODE) \

+ (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \

+ || (MODE) == V8SFmode || (MODE) == V4DFmode))

#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))

#define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)

@@ -1584,7 +1593,7 @@ typedef struct ix86_args {

int maybe_vaarg; /* true for calls to possibly vardic fncts. */

int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should

be passed in SSE registers. Otherwise 0. */

- int call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise

+ enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise

MS_ABI for ms abi. */

} CUMULATIVE_ARGS;

@@ -1618,9 +1627,6 @@ typedef struct ix86_args {

#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \

function_arg (&(CUM), (MODE), (TYPE), (NAMED))

-#define TARGET_ASM_FILE_END ix86_file_end

-#define NEED_INDICATE_EXEC_STACK 0

/* Output assembler code to FILE to increment profiler label # LABELNO

for profiling a function entry. */

@@ -1652,14 +1658,7 @@ typedef struct ix86_args {

/* Length in units of the trampoline for entering a nested function. */

-#define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)

-/* Emit RTL insns to initialize the variable parts of a trampoline.

- FNADDR is an RTX for the address of the function's pure code.

- CXT is an RTX for the static chain value for the function. */

-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \

- x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))

+#define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10)

/* Definitions for register eliminations.

@@ -1680,11 +1679,6 @@ typedef struct ix86_args {

{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \

{ FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \

-/* Given FROM and TO register numbers, say whether this elimination is

- allowed. */

-#define CAN_ELIMINATE(FROM, TO) ix86_can_eliminate ((FROM), (TO))

/* Define the offset between two registers, one to be eliminated, and the other

its replacement, at the start of a routine. */

@@ -1752,12 +1746,12 @@ typedef struct ix86_args {

#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)

#endif

-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression

+/* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression

that is a valid memory address for an instruction.

The MODE argument is the machine mode for the MEM expression

that wants to use this address.

- The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,

+ The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P,

except for CONSTANT_ADDRESS_P which is usually machine-independent.

See legitimize_pic_address in i386.c for details as to what

@@ -1772,22 +1766,6 @@ typedef struct ix86_args {

#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)

-#ifdef REG_OK_STRICT

-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \

-do { \

- if (legitimate_address_p ((MODE), (X), 1)) \

- goto ADDR; \

-} while (0)

-#else

-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \

-do { \

- if (legitimate_address_p ((MODE), (X), 0)) \

- goto ADDR; \

-} while (0)

-#endif

/* If defined, a C expression to determine the base term of address X.

This macro is used in only one place: `find_base_term' in alias.c.

@@ -1799,34 +1777,6 @@ do { \

#define FIND_BASE_TERM(X) ix86_find_base_term (X)

-/* Try machine-dependent ways of modifying an illegitimate address

- to be legitimate. If we find one, return the new, valid address.

- This macro is used in only one place: `memory_address' in explow.c.

- OLDX is the address as it was before break_out_memory_refs was called.

- In some cases it is useful to look at this to decide what needs to be done.

- MODE and WIN are passed so that this macro can use

- GO_IF_LEGITIMATE_ADDRESS.

- It is always safe for this macro to do nothing. It exists to recognize

- opportunities to optimize the output.

- For the 80386, we handle X+REG by loading X into a register R and

- using R+REG. R will go in a general reg and indexing will be used.

- However, if REG is a broken-out memory address or multiplication,

- nothing needs to be done because REG can certainly go in a general reg.

- When -fpic is used, special handling is needed for symbolic references.

- See comments by legitimize_pic_address in i386.c for details. */

-#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \

-do { \

- (X) = legitimize_address ((X), (OLDX), (MODE)); \

- if (memory_address_p ((MODE), (X))) \

- goto WIN; \

-} while (0)

/* Nonzero if the constant value X is a legitimate general operand

when generating PIC code. It is given that flag_pic is on and

that X satisfies CONSTANT_P or is a CONST_DOUBLE. */

@@ -1837,13 +1787,6 @@ do { \

(GET_CODE (X) == SYMBOL_REF \

|| GET_CODE (X) == LABEL_REF \

|| (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))

-/* Go to LABEL if ADDR (a legitimate address expression)

- has an effect that depends on the machine mode it is used for.

- On the 80386, only postdecrement and postincrement address depend thus

- (the amount of decrement or increment being the length of the operand).

- These are now caught in recog.c. */

-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)

/* Max number of args passed in registers. If this is more than 3, we will

have problems with ebx (register #4), since it is a caller save register and

@@ -1852,20 +1795,22 @@ do { \

/* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */

#define X86_64_REGPARM_MAX 6

-#define X64_REGPARM_MAX 4

-#define X86_32_REGPARM_MAX 3

+#define X86_64_MS_REGPARM_MAX 4

-#define X86_64_SSE_REGPARM_MAX 8

-#define X64_SSE_REGPARM_MAX 4

-#define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? 3 : 0)

+#define X86_32_REGPARM_MAX 3

#define REGPARM_MAX \

- (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X64_REGPARM_MAX \

+ (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X86_64_MS_REGPARM_MAX \

: X86_64_REGPARM_MAX) \

: X86_32_REGPARM_MAX)

+#define X86_64_SSE_REGPARM_MAX 8

+#define X86_64_MS_SSE_REGPARM_MAX 4

+#define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0)

#define SSE_REGPARM_MAX \

- (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X64_SSE_REGPARM_MAX \

+ (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X86_64_MS_SSE_REGPARM_MAX \

: X86_64_SSE_REGPARM_MAX) \

: X86_32_SSE_REGPARM_MAX)

@@ -2175,6 +2120,22 @@ do { \

#define ASM_OUTPUT_OPCODE(STREAM, PTR) \

ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR))

+/* A C statement to output to the stdio stream FILE an assembler

+ command to pad the location counter to a multiple of 1<<LOG

+ bytes if it is within MAX_SKIP bytes. */

+#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN

+#undef ASM_OUTPUT_MAX_SKIP_PAD

+#define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \

+ if ((LOG) != 0) \

+ { \

+ if ((MAX_SKIP) == 0) \

+ fprintf ((FILE), "\t.p2align %d\n", (LOG)); \

+ else \

+ fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \

+ }

+#endif

/* Under some conditions we need jump tables in the text section,

because the assembler cannot handle label differences between

sections. This is the case for x86_64 on Mach-O for example. */

@@ -2186,9 +2147,12 @@ do { \

/* Switch to init or fini section via SECTION_OP, emit a call to FUNC,

and switch back. For x86 we do this only to save a few bytes that

would otherwise be unused in the text section. */

-#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \

- asm (SECTION_OP "\n\t" \

- "call " USER_LABEL_PREFIX #FUNC "\n" \

+#define CRT_MKSTR2(VAL) #VAL

+#define CRT_MKSTR(x) CRT_MKSTR2(x)

+#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \

+ asm (SECTION_OP "\n\t" \

+ "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \

TEXT_SECTION_ASM_OP);

/* Print operand X (an rtx) in assembler syntax to file FILE.

@@ -2230,6 +2194,7 @@ enum processor_type

PROCESSOR_GENERIC32,

PROCESSOR_GENERIC64,

PROCESSOR_AMDFAM10,

+ PROCESSOR_ATOM,

PROCESSOR_max

};

@@ -2286,7 +2251,12 @@ extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];

extern rtx ix86_compare_op0; /* operand 0 for comparisons */

extern rtx ix86_compare_op1; /* operand 1 for comparisons */

-extern rtx ix86_compare_emitted;

+enum ix86_fpcmp_strategy {

+ IX86_FPCMP_SAHF,

+ IX86_FPCMP_COMI,

+ IX86_FPCMP_ARITH

+};

/* To properly truncate FP values into integers, we need to set i387 control

word. We can't emit proper mode switching code before reload, as spills

@@ -2376,21 +2346,43 @@ enum ix86_stack_slot

#define FASTCALL_PREFIX '@'

-struct machine_function GTY(())

+/* Machine specific CFA tracking during prologue/epilogue generation. */

+#ifndef USED_FOR_TARGET

+struct GTY(()) machine_cfa_state

{

+ rtx reg;

+ HOST_WIDE_INT offset;

+};

+struct GTY(()) machine_function {

struct stack_local_entry *stack_locals;

const char *some_ld_name;

int varargs_gpr_size;

int varargs_fpr_size;

- int accesses_prev_frame;

int optimize_mode_switching[MAX_386_ENTITIES];

- int needs_cld;

+ /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE

+ has been computed for. */

+ int use_fast_prologue_epilogue_nregs;

+ /* The CFA state at the end of the prologue. */

+ struct machine_cfa_state cfa;

+ /* This value is used for amd64 targets and specifies the current abi

+ to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */

+ enum calling_abi call_abi;

+ /* Nonzero if the function accesses a previous frame. */

+ BOOL_BITFIELD accesses_prev_frame : 1;

+ /* Nonzero if the function requires a CLD in the prologue. */

+ BOOL_BITFIELD needs_cld : 1;

/* Set by ix86_compute_frame_layout and used by prologue/epilogue

expander to determine the style used. */

- int use_fast_prologue_epilogue;

- /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed

- for. */

- int use_fast_prologue_epilogue_nregs;

+ BOOL_BITFIELD use_fast_prologue_epilogue : 1;

/* If true, the current function needs the default PIC register, not

an alternate register (on x86) and must not use the red zone (on

x86_64), even if it's a leaf function. We don't want the

@@ -2400,11 +2392,13 @@ struct machine_function GTY(())

if all such instructions are optimized away. Use the

ix86_current_function_calls_tls_descriptor macro for a better

approximation. */

- int tls_descriptor_call_expanded_p;

- /* This value is used for amd64 targets and specifies the current abi

- to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */

- int call_abi;

+ BOOL_BITFIELD tls_descriptor_call_expanded_p : 1;

+ /* If true, the current function has a STATIC_CHAIN is placed on the

+ stack below the return address. */

+ BOOL_BITFIELD static_chain_on_stack : 1;

};

+#endif

#define ix86_stack_locals (cfun->machine->stack_locals)

#define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size)

@@ -2420,6 +2414,8 @@ struct machine_function GTY(())

REG_SP is live. */

#define ix86_current_function_calls_tls_descriptor \

(ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))

+#define ix86_cfa_state (&cfun->machine->cfa)

+#define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack)

/* Control behavior of x86_file_start. */

#define X86_FILE_START_VERSION_DIRECTIVE false

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