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Unified Diff: gcc/gcc/config/i386/i386.opt

Issue 3050029: [gcc] GCC 4.5.0=>4.5.1 (Closed) Base URL: ssh://git@gitrw.chromium.org:9222/nacl-toolchain.git
Patch Set: Created 10 years, 5 months ago
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Index: gcc/gcc/config/i386/i386.opt
diff --git a/gcc/gcc/config/i386/i386.opt b/gcc/gcc/config/i386/i386.opt
index 853059081d2de90a75cb66c035fd2dd459ee0480..0afdd1197f613bd4222fd8468e19b7d2dc17e68e 100644
--- a/gcc/gcc/config/i386/i386.opt
+++ b/gcc/gcc/config/i386/i386.opt
@@ -228,6 +228,10 @@ mtune=
Target RejectNegative Joined Var(ix86_tune_string)
Schedule code for given CPU
+mabi=
+Target RejectNegative Joined Var(ix86_abi_string)
+Generate code that conforms to the given ABI
+
mveclibabi=
Target RejectNegative Joined Var(ix86_veclibabi_string)
Vector library ABI to use
@@ -240,11 +244,8 @@ mcld
Target Report Mask(CLD) Save
Generate cld instruction in the function prologue.
-mno-fused-madd
-Target RejectNegative Report Mask(NO_FUSED_MADD) Undocumented Save
-
mfused-madd
-Target Report InverseMask(NO_FUSED_MADD, FUSED_MADD) Save
+Target Report Mask(FUSED_MADD) Save
Enable automatic generation of fused floating point multiply-add instructions
if the ISA supports such instructions. The -mfused-madd option is on by
default.
@@ -315,9 +316,17 @@ msse4a
Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) VarExists Save
Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
-msse5
-Target Report Mask(ISA_SSE5) Var(ix86_isa_flags) VarExists Save
-Support SSE5 built-in functions and code generation
+mfma4
+Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) VarExists Save
+Support FMA4 built-in functions and code generation
+
+mxop
+Target Report Mask(ISA_XOP) Var(ix86_isa_flags) VarExists Save
+Support XOP built-in functions and code generation
+
+mlwp
+Target Report Mask(ISA_LWP) Var(ix86_isa_flags) VarExists Save
+Support LWP built-in functions and code generation
mabm
Target Report Mask(ISA_ABM) Var(ix86_isa_flags) VarExists Save
@@ -335,6 +344,14 @@ msahf
Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) VarExists Save
Support code generation of sahf instruction in 64bit x86-64 code.
+mmovbe
+Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) VarExists Save
+Support code generation of movbe instruction.
+
+mcrc32
+Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) VarExists Save
+Support code generation of crc32 instruction.
+
maes
Target Report Mask(ISA_AES) Var(ix86_isa_flags) VarExists Save
Support AES built-in functions and code generation
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