| Index: gcc/gcc/config/sh/sh.opt
|
| diff --git a/gcc/gcc/config/sh/sh.opt b/gcc/gcc/config/sh/sh.opt
|
| index 9aaba6c151ef310819c850506b25ab8df73b8579..dbe077ca49bc69c40c2e151c896a1838dc41de49 100644
|
| --- a/gcc/gcc/config/sh/sh.opt
|
| +++ b/gcc/gcc/config/sh/sh.opt
|
| @@ -1,6 +1,6 @@
|
| ; Options for the SH port of the compiler.
|
|
|
| -; Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
|
| +; Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
|
| ;
|
| ; This file is part of GCC.
|
| ;
|
| @@ -49,7 +49,7 @@ Generate SH2 code
|
|
|
| m2a
|
| Target RejectNegative Condition(SUPPORT_SH2A)
|
| -Generate SH2a code
|
| +Generate default double-precision SH2a-FPU code
|
|
|
| m2a-nofpu
|
| Target RejectNegative Condition(SUPPORT_SH2A_NOFPU)
|
| @@ -57,11 +57,11 @@ Generate SH2a FPU-less code
|
|
|
| m2a-single
|
| Target RejectNegative Condition(SUPPORT_SH2A_SINGLE)
|
| -Generate default single-precision SH2a code
|
| +Generate default single-precision SH2a-FPU code
|
|
|
| m2a-single-only
|
| Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY)
|
| -Generate only single-precision SH2a code
|
| +Generate only single-precision SH2a-FPU code
|
|
|
| m2e
|
| Target RejectNegative Condition(SUPPORT_SH2E)
|
| @@ -224,13 +224,9 @@ mcbranchdi
|
| Target Var(TARGET_CBRANCHDI4)
|
| Enable cbranchdi4 pattern
|
|
|
| -mexpand-cbranchdi
|
| -Target Var(TARGET_EXPAND_CBRANCHDI4)
|
| -Expand cbranchdi4 pattern early into separate comparisons and branches.
|
| -
|
| mcmpeqdi
|
| Target Var(TARGET_CMPEQDI_T)
|
| -Emit cmpeqdi_t pattern even when -mcbranchdi and -mexpand-cbranchdi are in effect.
|
| +Emit cmpeqdi_t pattern even when -mcbranchdi is in effect.
|
|
|
| mcut2-workaround
|
| Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND)
|
| @@ -248,13 +244,14 @@ mdivsi3_libfunc=
|
| Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("")
|
| Specify name for 32 bit signed division function
|
|
|
| +mfmovd
|
| +Target RejectNegative Mask(FMOVD)
|
| +Enable the use of 64-bit floating point registers in fmov instructions. See -mdalign if 64-bit alignment is required.
|
| +
|
| mfixed-range=
|
| Target RejectNegative Joined Var(sh_fixed_range_str)
|
| Specify range of registers to make fixed
|
|
|
| -mfmovd
|
| -Target RejectNegative Mask(FMOVD) Undocumented
|
| -
|
| mfused-madd
|
| Target Var(TARGET_FMAC)
|
| Enable the use of the fused floating point multiply-accumulate operation
|
| @@ -319,7 +316,7 @@ Follow Renesas (formerly Hitachi) / SuperH calling conventions
|
|
|
| mspace
|
| Target Report RejectNegative Mask(SMALLCODE)
|
| -Deprecated. Use -Os instead
|
| +Deprecated. Use -Os instead
|
|
|
| multcost=
|
| Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1)
|
|
|