[gcc] GCC 4.5.0=>4.5.1

gcc/gcc/config/arm/neon.ml

Index: gcc/gcc/config/arm/neon.ml
diff --git a/gcc/gcc/config/arm/neon.ml b/gcc/gcc/config/arm/neon.ml
index 10393b33ebcb7116d7f446411e358abbf8e2af7e..f77f05cc825537186024ebf552d214a74ab5a9ba 100644
--- a/gcc/gcc/config/arm/neon.ml
+++ b/gcc/gcc/config/arm/neon.ml
@@ -1,7 +1,7 @@
 (* Common code for ARM NEON header file, documentation and test case
    generators.
 
-   Copyright (C) 2006, 2007 Free Software Foundation, Inc.
+   Copyright (C) 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
    Contributed by CodeSourcery.
 
    This file is part of GCC.
@@ -50,7 +50,7 @@ type vectype = T_int8x8    | T_int8x16
              | T_ptrto of vectype | T_const of vectype
              | T_void      | T_intQI
              | T_intHI     | T_intSI
-             | T_intDI
+             | T_intDI     | T_floatSF
 
 (* The meanings of the following are:
      TImode : "Tetra", two registers (four words).
@@ -68,6 +68,7 @@ type shape_elt = Dreg | Qreg | Corereg | Immed | VecArray of int * shape_elt
 	       | Element_of_dreg	(* Used for "lane" variants.  *)
 	       | Element_of_qreg	(* Likewise.  *)
 	       | All_elements_of_dreg	(* Used for "dup" variants.  *)
+	       | Alternatives of shape_elt list (* Used for multiple valid operands *)
 
 type shape_form = All of int * shape_elt
                 | Long
@@ -233,6 +234,7 @@ type features =
        cases.  The function supplied must return the integer to be written
        into the testcase for the argument number (0-based) supplied to it.  *)
   | Const_valuator of (int -> int)
+  | Fixed_return_reg
 
 exception MixedMode of elts * elts
 
@@ -1008,7 +1010,10 @@ let ops =
       pf_su_8_64;
 
     (* Set all lanes to the same value.  *)
-    Vdup_n, [],
+    Vdup_n,
+      [Disassembles_as [Use_operands [| Dreg;
+                                        Alternatives [ Corereg;
+                                                       Element_of_dreg ] |]]],
       Use_operands [| Dreg; Corereg |], "vdup_n", bits_1,
       pf_su_8_32;
     Vdup_n,
@@ -1016,7 +1021,10 @@ let ops =
        Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]],
       Use_operands [| Dreg; Corereg |], "vdup_n", notype_1,
       [S64; U64];
-    Vdup_n, [],
+    Vdup_n,
+      [Disassembles_as [Use_operands [| Qreg;
+                                        Alternatives [ Corereg;
+                                                       Element_of_dreg ] |]]],
       Use_operands [| Qreg; Corereg |], "vdupQ_n", bits_1,
       pf_su_8_32;
     Vdup_n,
@@ -1028,7 +1036,10 @@ let ops =
 
     (* These are just aliases for the above.  *)
     Vmov_n,
-      [Builtin_name "vdup_n"],
+      [Builtin_name "vdup_n";
+       Disassembles_as [Use_operands [| Dreg;
+                                        Alternatives [ Corereg;
+                                                       Element_of_dreg ] |]]],
       Use_operands [| Dreg; Corereg |],
       "vmov_n", bits_1, pf_su_8_32;
     Vmov_n,
@@ -1038,7 +1049,10 @@ let ops =
       Use_operands [| Dreg; Corereg |],
       "vmov_n", notype_1, [S64; U64];
     Vmov_n,
-      [Builtin_name "vdupQ_n"],
+      [Builtin_name "vdupQ_n";
+       Disassembles_as [Use_operands [| Qreg;
+                                        Alternatives [ Corereg;
+                                                       Element_of_dreg ] |]]],
       Use_operands [| Qreg; Corereg |],
       "vmovQ_n", bits_1, pf_su_8_32;
     Vmov_n,
@@ -1076,9 +1090,13 @@ let ops =
       Use_operands [| Dreg; Qreg |], "vget_high",
       notype_1, pf_su_8_64;
     Vget_low, [Instruction_name ["vmov"];
-               Disassembles_as [Use_operands [| Dreg; Dreg |]]],
+               Disassembles_as [Use_operands [| Dreg; Dreg |]];
+	       Fixed_return_reg],
       Use_operands [| Dreg; Qreg |], "vget_low",
-      notype_1, pf_su_8_64;
+      notype_1, pf_su_8_32;
+     Vget_low, [No_op],
+      Use_operands [| Dreg; Qreg |], "vget_low",
+      notype_1, [S64; U64];
 
     (* Conversions.  *)
     Vcvt, [InfoWord], All (2, Dreg), "vcvt", conv_1,
@@ -1693,6 +1711,7 @@ let string_of_vectype vt =
   | T_intHI -> "__builtin_neon_hi"
   | T_intSI -> "__builtin_neon_si"
   | T_intDI -> "__builtin_neon_di"
+  | T_floatSF -> "__builtin_neon_sf"
   | T_arrayof (num, base) ->
       let basename = name (fun x -> x) base in
       affix (Printf.sprintf "%sx%d" basename num)